Philips Semiconductors
Product specification
10-bit transparent latch with 5-volt tolerant
inputs/outputs (3-State)
74LVC841A
FEATURES
•
5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
•
Wide supply voltage range of 1.2 V to 3.6 V
•
In accordance with the JEDEC standard no. 8-1 A
•
Inputs accept voltages up to 5.5 V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Flow-through pin-out architecture
DESCRIPTION
The 74LVC841A is a low-power, low-voltage, Si-gate CMOS device
and superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. In 3-State
operation, outputs can handle 5 V. This feature allows the use of
these devices as translators in a mixed 3.3 V/5 V environment. The
74LVC841A is a 10-bit transparent latch featuring separate D-type
inputs for each latch and 3-State outputs for bus oriented
applications. A latch enable (LE) input and an output enable (OE)
input are common to all internal latches. The 74LVC841A consists of
ten transparent latches with 3-State true outputs. When LE is HIGH,
data at the D
n
inputs enters the latches. In this condition the latches
are transparent, i.e., a latch output will change each time its
corresponding D-input changes. When LE is LOW the latches store
the information that was present at the D-inputs a set-up time
preceding the HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the ten latches are available at the outputs.
When OE is HIGH, the outputs go to the high impedance OFF-state.
Operation of the OE input does not affect the state of the latches.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25°C; t
r
=t
f
≤
2.5 ns
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
PARAMETER
Propagation delay
D
n
to Q
n
;
LE to Q
n
Input capacitance
Power dissipation capacitance per latch
V
I
= GND to V
CC1
CONDITIONS
C
L
= 50 pF;
V
CC
= 3.3 V
TYPICAL
4.5
5.0
5.0
22
UNIT
ns
pF
pF
NOTE:
1 C
PD
is used to determine the dynamic power dissipation (P
D
in
µW)
P
D
= C
PD
×
V
CC2
×
f
i
)
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
24-Pin Plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
OUTSIDE NORTH AMERICA
74LVC841A D
74LVC841A DB
74LVC841A PW
NORTH AMERICA
74LVC841A D
74LVC841A DB
7LVC841APW DH
PKG. DWG. #
SOT137-1
SOT340-1
SOT355-1
PIN CONFIGURATION
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
1
2
3
4
5
6
7
8
9
10
11
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q
8
Q
9
LE
PIN DESCRIPTION
PIN NUMBER
1
2, 3, 4, 5, 6, 7, 8,
9, 10, 11
SYMBOL
OE
D
0
to D
9
NAME AND FUNCTION
Output enable input (active Low)
Data inputs
3-state latch outputs
Ground (0 V)
Latch enable input (active HIGH)
Positive supply voltage
23, 22, 21, 20, 19,
Q
0
to Q
9
18, 17, 16, 15, 14
12
13
24
GND
LE
V
CC
GND 12
SV01723
1998 Jun 17
2
853-2071 19589
Philips Semiconductors
Product specification
10-bit transparent latch with 5-volt tolerant
inputs/outputs (3-State)
74LVC841A
LOGIC SYMBOL (IEEE/IEC)
13
LOGIC SYMBOL
13
1
C1
EN
2
3
4
5
6
7
8
9
10
11
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
LE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
23
22
21
3
20
4
19
5
18
6
17
7
16
8
15
9
14
10
11
15
14
16
17
18
19
20
21
22
2
1D
23
OE
Q9
1
SV01724
SV01725
LOGIC DIAGRAM
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LE LE
LE
OE
LATCH
2
LE LE
LATCH
3
LE LE
LATCH
4
LE LE
LATCH
5
LE LE
LATCH
6
LE LE
LATCH
7
LE LE
LATCH
8
LE LE
LATCH
9
LE LE
LATCH
10
LE LE
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q
8
Q
9
SV01726
FUNCTION TABLE for register A
n
or B
n
INPUTS
OPERATING MODES
Enable and read register (transparent mode)
Latch and read register
latch register and disable outputs
Hold
OE
L
L
L
L
H
H
L
LE
H
H
↓
↓
X
X
L
D
n
L
H
l
h
l
h
X
INTERNAL
LATCHES
L
H
L
H
L
H
NC
OUTPUTS
Q
0
TO Q
9
L
H
L
H
Z
Z
NC
NOTES:
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l
= LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
X = don’t care
Z = high impedance OFF-state
NC = no change
1998 Jun 17
3
Philips Semiconductors
Product specification
10-bit transparent latch with 5-volt tolerant
inputs/outputs (3-State)
74LVC841A
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
O
T
amb
t
r
, t
f
PARAMETER
DC supply voltage (for max. speed performance)
DC supply voltage (for low-voltage applications)
DC input voltage range
DC output voltage range
Operating free-air temperature range
Input rise and fall times
V
CC
= 1.2 to 2.7V
V
CC
= 2.7 to 3.6V
CONDITIONS
LIMITS
MIN
2.7
1.2
0
0
–40
0
0
MAX
3.6
3.6
5.5
V
CC
+85
20
10
UNIT
V
V
V
°C
ns/V
ABSOLUTE MAXIMUM RATINGS
NO TAG
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
GND
, I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or GND current
Storage temperature range
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
V
I
t
0
Note NO TAG
V
O
uV
CC
or V
O
t
0
Note NO TAG
V
O
= 0 to V
CC
CONDITIONS
RATING
–0.5 to +6.5
–50
–0.5 to +5.5
"50
–0.5 to V
CC
+0.5
"50
"100
–65 to +150
500
500
UNIT
V
mA
V
mA
V
mA
mA
°C
mW
NOTES:
1 Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2 The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jun 17
4
Philips Semiconductors
Product specification
10-bit transparent latch with 5-volt tolerant
inputs/outputs (3-State)
74LVC841A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
V
CC
= 1.2V
V
CC
= 2.7 to 3.6V
V
CC
= 1.2V
V
CC
= 2.7 to 3.6V
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= –12mA
V
OH
HIGH level output voltage
out ut
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= –100µA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= –18mA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= –24mA
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= 12mA
V
OL
I
I
I
OZ
I
CC
∆I
CC
LOW level output voltage
In ut
Input leakage current
3-State output OFF-state current
Quiescent supply current
Additional quiescent supply current per
input pin
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= 100µA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 24mA
V
CC
= 3 6V; V
I
= 5 5V or GND
3.6V;
5.5V
V
CC
= 3.6V; V
I
= V
IH
or V
IL
; V
O
= V
CC
or GND
V
CC
= 3.6V; V
I
= V
CC
or GND; I
O
= 0
V
CC
= 2.7V to 3.6V; V
I
= V
CC
–0.6V; I
O
= 0
"0.1
"0
1
0.1
0.1
5
GND
V
CC
*0.5
V
CC
*0.2
V
CC
*0.6
V
CC
*1.0
0.40
0.20
0.55
"5
"5
10
500
µA
µA
µA
µA
V
V
CC
V
TEST CONDITIONS
Temp = -40°C to +85°C
MIN
V
IH
V
IL
HIGH level Input voltage
In ut
LOW level In ut voltage
Input
V
CC
2.0
GND
0.8
TYP
1
MAX
V
V
UNIT
NOTE:
1 All typical values are at V
CC
= 3.3V and T
amb
= 25°C.
AC CHARACTERISTICS
GND = 0 V; t
r
= t
f
v
2.5 ns; C
L
= 50 pF; R
L
= 500W; T
amb
= –40_C to +85_C
LIMITS
SYMBOL
PARAMETER
Propagation delay
D
n
to Q
n
Propagation delay
LE to Q
n
3-state output enable time
OE to Q
n
3-state output disable time
OE to Q
n
LE pulse width, HIGH
Set-up time
D
n
to LE
Hold time
D
n
to LE
WAVEFORM
MIN
t
PHL
/t
PLH
t
PHL/
t
PLH
t
PZH/
t
PZL
t
PHZ/
t
PLZ
t
w
t
su
t
h
Figures NO TAG,
NO TAG
Figures NO TAG,
NO TAG
Figures 3, NO TAG
Figures 3, NO TAG
Figure 4
Figure 4
Figure 4
1.5
1.5
1.5
1.5
2.0
2.0
1.0
V
CC
= 3.3V
±0.3V
TYP
1
4.5
4.9
5.4
3.8
0.7
0.5
–0.5
MAX
6.7
7.6
7.9
5.9
–
–
–
V
CC
= 2.7V
MIN
1.5
1.5
1.5
1.5
2.0
2.0
1.0
MAX
7.5
8.6
8.9
6.9
ns
ns
ns
ns
ns
ns
ns
UNIT
NOTE:
1 All typical values are at V
CC
= 3.3V and T
amb
= 25°C.
1998 Jun 17
5
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