54ACT 74ACT825 8-Bit D Flip-Flop
March 1993
54ACT 74ACT825
8-Bit D Flip-Flop
General Description
The ’ACT825 is an 8-bit buffered register They have Clock
Enable and Clear features which are ideal for parity bus
interfacing in high performance microprogramming systems
Also included are multiple enables that allow multi-use con-
trol of the interface The ’ACT825 has noninverting outputs
and is fully compatible with AMD’s Am29825
Features
Y
Y
Y
Y
Outputs source sink 24 mA
Inputs and outputs are on opposite sides
’ACT825 has TTL-compatible inputs
Standard Military Drawing (SMD)
’ACT825 5962-91611
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP Flatpak and SOIC
IEEE IEC
TL F 9895–1
TL F 9895 – 2
TL F 9895 – 3
Pin Names
D
0
–D
7
O
0
–O
7
OE
1
OE
2
OE
3
EN
CLR
CP
Description
Data Inputs
Data Outputs
Output Enables
Clock Enable
Clear
Clock Input
Pin Assignment
for LCC
TL F 9895 – 4
FACT
TM
is a trademark of National Semiconductor
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9895
RRD-B30M75 Printed in U S A
Functional Description
The ’ACT825 consists of eight D-type edge-triggered flip-
flops These devices have TRI-STATE outputs for bus sys-
tems organized in a broadside pinning In addition to the
clock and output enable pins the buffered clock (CP) and
buffered Output Enable (OE) are common to all flip-flops
The flip-flops will store the state of their individual D inputs
that meet the setup and hold time requirements on the
LOW-to-HIGH CP transition With OE
1
OE
2
and OE
3
LOW
the contents of the flip-flops are available at the outputs
When one of OE
1
OE
2
or OE
3
is HIGH the outputs go to
the high impedance state
Function Table
Inputs
OE
H
H
H
L
H
L
H
H
L
L
CLR
X
X
L
L
H
H
H
H
H
H
EN
L
L
X
X
H
H
L
L
L
L
CP
L
L
X
X
X
X
L
L
L
L
D
n
L
H
X
X
X
X
L
H
L
H
Internal
Q
L
H
L
L
NC
NC
L
H
L
H
Output
O
Z
Z
Z
L
Z
NC
Z
Z
L
H
High-Z
High-Z
Clear
Clear
Hold
Hold
Load
Load
Load
Load
Function
Operation of the OE input does not affect the state of the
flip-flops The ’ACT825 has Clear (CLR) and Clock Enable
(EN) pins These pins are ideal for parity bus interfacing in
high performance systems
When CLR is LOW and OE is LOW the outputs are LOW
When CLR is HIGH data can be entered into the flip-flops
When EN is LOW data on the inputs is transferred to the
outputs on the LOW-to-HIGH clock transition When EN is
HIGH the outputs do not change state regardless of the
data or clock input transitions
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Z
e
High Impedance
L
e
LOW-to-HIGH Transition
NC
e
No Change
Logic Diagram
TL F 9895 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
e b
0 5V
V
I
e
V
CC
a
0 5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
e b
0 5V
V
O
e
V
CC
a
0 5V
DC Output Voltage (V
O
)
DC Output Source or Sink Current (I
O
)
DC V
CC
or Ground Current
Per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
Junction Temperature (T
J
)
CDIP
PDIP
b
0 5V to 7 0V
b
20 mA
a
20 mA
b
0 5V to V
CC
a
0 5V
b
20 mA
a
20 mA
a
0 5V
g
50 mA
g
50 mA
Recommended Operating
Conditions
Supply Voltage (V
CC
)
’ACT
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
74ACT
54ACT
Minimum Input Edge Rate (DV
Dt)
’ACT Devices
V
IN
from 0 8V to 2 0V
V
CC
4 5V 5 5V
4 5V to 5 5V
0V to V
CC
0V to V
CC
b
40 C to
a
85 C
b
55 C to
a
125 C
125 mV ns
b
65 C to
a
150 C
175 C
140 C
Note 1
Absolute maximum ratings are those values beyond which damage
to the device may occur The databook specifications should be met without
exception to ensure that the system design is reliable over its power supply
temperature and output input loading variables National does not recom-
mend operation of FACT
TM
circuits outside databook specifications
DC Electrical Characteristics
74ACT
Symbol
Parameter
V
CC
(V)
T
A
e
25 C
Typ
V
IH
V
IL
V
OH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
45
55
45
55
45
55
45
55
V
OL
Maximum Low Level
Output Voltage
4 5 0 001
5 5 0 001
45
55
I
IN
I
OZ
I
CCT
I
OLD
I
OHD
I
CC
Maximum Input Leakage Current 5 5
Maximum TRI-STATE Current
Maximum I
CC
Input
Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
55
55
55
55
55
80
06
15
15
15
15
4 49
5 49
20
20
08
08
44
54
3 86
4 86
01
01
0 36
0 36
g
0 1
g
0 5
54ACT
74ACT
Conditions
T
A
e
T
A
e
Units
b
55 C to
a
125 C
b
40 C to
a
85 C
Guaranteed Limits
20
20
08
08
44
54
3 70
4 70
01
01
0 50
0 50
g
1 0
g
10 0
20
20
08
08
44
54
3 76
4 76
01
01
0 44
0 44
g
1 0
g
5 0
V
V
OUT
e
0 1V
or V
CC
b
0 1V
V
OUT
e
0 1V
or V
CC
b
0 1V
V
I
OUT
e b
50
mA
V
IN
e
V
IL
or V
IH
b
24 mA
I
OH
b
24 mA
I
OUT
e
50
mA
V
IN
e
V
IL
or V
IH
I
OL
24 mA
24 mA
V
I
e
V
CC
GND
V
I
e
V
IL
V
IH
V
O
e
V
CC
GND
V
I
e
V
CC
b
2 1V
V
OLD
e
1 65V Max
V
OHD
e
3 85V Min
V
IN
e
V
CC
or GND
V
V
V
mA
mA
mA
mA
mA
mA
16
50
b
50
15
75
b
75
160
80
All outputs loaded thresholds on input associated with output under test
Maximum test duration 2 0 ms one output loaded at a time
Note
I
CC
limit for 54ACT
25 C is identical to 74ACT
25 C
3
AC Electrical Characteristics
74ACT
Symbol
Parameter
V
CC
(V)
Min
f
max
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum Clock
Frequency
Propagation Delay
CP to O
n
Propagation Delay
CP to O
n
Propagation Delay
CLR to O
n
Output Enable Time
OE to O
n
Output Enable Time
OE to O
n
Output Disable Time
OE to O
n
Output Disable Time
OE to O
n
50
50
50
50
50
50
50
50
120
15
20
25
15
20
15
15
T
A
e a
25 C
C
L
e
50 pF
Typ
158
55
55
80
60
65
65
60
95
95
13 5
10 5
11 0
11 0
10 5
Max
54ACT
T
A
e b
55 C
to
a
125 C
C
L
e
50 pF
Min
95
15
15
15
15
15
15
15
11 5
11 5
18 0
11 5
12 5
13 5
13 0
Max
74ACT
T
A
e b
40 C
to
a
85 C
C
L
e
50 pF
Min
109
15
15
20
15
15
15
15
10 5
10 5
15 5
11 5
12 0
12 0
11 5
Max
MHz
ns
ns
ns
ns
ns
ns
ns
Units
Voltage Range 5 0 is 5 0V
g
0 5V
AC Operating Requirements
74ACT
Symbol
Parameter
V
CC
(V)
T
A
e a
25 C
C
L
e
50 pF
Typ
t
s
t
h
t
s
t
h
t
w
t
w
t
rec
Setup Time HIGH or LOW
D
n
to CP
Hold Time HIGH or LOW
D
n
to CP
Setup Time HIGH or LOW
EN to CP
Hold Time HIGH or LOW
EN to CP
CP Pulse Width
HIGH or LOW
CLR Pulse Width LOW
CLR to CP
Recovery Time
50
50
50
50
50
50
50
05
0
0
0
25
30
15
25
25
20
10
45
55
35
54ACT
T
A
e b
55 C
to
a
125 C
C
L
e
50 pF
74ACT
T
A
e b
40 C
to
a
85 C
C
L
e
50 pF
Units
Guaranteed Minimum
40
25
40
20
60
70
45
25
25
25
10
55
55
40
ns
ns
ns
ns
ns
ns
ns
Voltage Range 5 0 is 5 0V
g
0 5V
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation
Capacitance
Typ
45
44
Units
pF
pF
Conditions
V
CC
e
OPEN
V
CC
e
5 0V
4
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows
74ACT
Temperature Range Family
74ACT
e
Commercial TTL-Compatible
54ACT
e
Military TTL-Compatible
Device Type
Package Code
SP
e
Slim Plastic DIP
SD
e
Slim Ceramic DIP
F
e
Flatpak
L
e
Leadless Ceramic Chip Carrier (LCC)
S
e
Small Outline (SOIC)
825
P
C
QR
Special Variations
X
e
Devices shipped in 13 reels
QR
e
Commercial grade device
with burn-in
QB
e
Military grade device with
environmental and burn-in
processing shipped in tubes
Temperature Range
C
e
Commercial (
b
40 C to
a
85 C)
M
e
Military (
b
55 C to
a
125 C)
Physical Dimensions
inches (millimeters)
28-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E28A
5
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