D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
74LVX574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
June 1993
Revised April 2005
74LVX574
Low Voltage Octal D-Type Flip-Flop with
3-STATE Outputs
General Description
The LVX574 is a high-speed octal D-type flip-flop which is
controlled by an edge-triggered clock input (CP) and a buff-
ered common Output Enable (OE) input. When the OE
input is HIGH, the eight outputs are in a high impedance
state. The LVX574 is functionally identical to the LVX374
but with inputs and outputs on opposite sides of the pack-
age. The inputs tolerate up to 7V allowing interface of 5V
systems to 3V systems.
Features
s
Input voltage translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX574M
74LVX574SJ
74LVX574MTC
Package Number
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
D
0
–D
7
CP
OE
O
0
–O
7
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
Description
© 2005 Fairchild Semiconductor Corporation
DS500050
www.fairchildsemi.com
74LVX574
Functional Description
The LVX574 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Truth Table
Inputs
D
n
H
L
X
CP
Outputs
OE
L
L
H
O
n
H
L
Z
X
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
74LVX574
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
0.5V to
7.0V
20 mA
0.5V to 7V
20 mA
20 mA
0.5V to V
CC
0.5V
r
25 mA
r
75 mA
65
q
C to
150
q
C
180 mW
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Input Rise and Fall Time (
'
t/
'
V)
2.0V to 3.6V
0V to 5.5V
0V to V
CC
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
V
O
40
q
C to
85
q
C
0 ns/V to 100 ns/V
0.5V
V
CC
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
(I
CC
or I
GND
)
Storage Temperature (T
STG
)
Power Dissipation
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level
Input Voltage
V
IL
LOW Level
Input Voltage
V
OH
HIGH Level
Output Voltage
V
OL
LOW Level
Output Voltage
I
OZ
I
IN
I
CC
3-STATE Output
Off-State Current
Input Leakage Current
Quiescent Supply Current
3.6
3.6
V
CC
2.0
3.0
3.6
2.0
3.0
3.6
2.0
3.0
3.0
2.0
3.0
3.0
3.6
1.9
2.9
2.58
0.0
0.0
0.1
0.1
0.36
2.0
3.0
T
A
Min
1.5
2.0
2.4
0.5
0.8
0.8
1.9
2.9
2.48
0.1
0.1
0.44
V
V
IN
V
IH
or V
IL
V
25
q
C
Typ
Max
T
A
40
q
C to
85
q
C
Min
1.5
2.0
2.4
0.5
0.8
0.8
Max
Units
Conditions
V
V
V
IN
V
IH
or V
IL
I
OH
I
OH
I
OH
I
OL
I
OL
I
OL
V
IN
V
OUT
V
IN
V
IN
V
IH
or V
IL
V
CC
or GND
5.5V or GND
V
CC
or GND
50
P
A
50
P
A
4 mA
50
P
A
50
P
A
4 mA
r
0.25
r
0.1
4.0
r
2.5
r
1.0
40.0
P
A
P
A
P
A
Noise Characteristics
(Note 3)
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
t
f
3 ns)
V
CC
(V)
3.3
3.3
3.3
3.3
T
A
Typ
0.5
25
q
C
Limit
0.8
Units
V
V
V
V
C
L
(pF)
50
50
50
50
0.5
0.8
2.0
0.8
Note 3:
(Input t
r
3
www.fairchildsemi.com
74LVX574
AC Electrical Characteristics
(Note 4)
Symbol
f
MAX
Parameter
Maximum
Clock
Frequency
t
PLH
t
PHL
Propagation
Delay Time
CP to O
n
t
PZL
t
PZH
3-STATE Output
Enable Time
3.3
r
0.3
t
PLZ
t
PHZ
t
W
t
S
t
H
t
OSHL
t
OSLH
3-STATE Output
Disable Time
CP Pulse
Width
Setup Time
D
n
to CP
Hold Time
D
n
to CP
Output to Output
Skew (Note 4)
2.7
3.3
r
0.3
2.7
3.3
r
0.3
2.7
3.3
r
0.3
2.7
3.3
r
0.3
2.7
3.3
|t
PLHm
t
PLHn
|, t
OSHL
V
CC
(V)
2.7
3.3
r
0.3
2.7
3.3
r
0.3
2.7
Min
60
45
80
50
T
A
25
q
C
Typ
115
60
125
75
9.2
11.5
8.5
11.0
9.8
11.4
8.2
10.7
12.1
11.0
14.5
18.0
13.2
16.7
15.0
18.5
12.8
16.3
19.1
15.0
Max
T
A
40
q
C to
85
q
C
Min
50
40
65
45
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
7.5
5.0
5.0
3.5
1.5
1.5
17.5
21.0
15.5
19.0
18.5
22.0
15.0
18.5
22.0
17.0
Max
Units
C
L
MHZ
C
L
C
L
C
L
C
L
ns
C
L
C
L
C
L
C
L
ns
C
L
C
L
C
L
ns
ns
ns
ns
C
L
C
L
Conditions
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF, R
L
50 pF, R
L
15 pF, R
L
50 pF, R
L
50 pF, R
L
50 pF, R
L
1 k
:
1 k
:
1 k
:
1 k
:
1 k
:
1 k
:
6.5
5.0
5.0
3.5
1.5
1.5
1.5
1.5
|t
PHLm
t
PHLn
|.
1.5
1.5
ns
C
L
50 pF
Note 4:
Parameter guaranteed by design. t
OSLH
Capacitance
Symbol
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance (Note 5)
Note 5:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Parameter
T
A
Min
25
q
C
Typ
4
6
27
Max
10
T
A
40
q
C to
85
q
C
Min
Max
10
Units
pF
pF
pF
www.fairchildsemi.com
4
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
