Low Voltage, Low Skew, 3.3V LVPECL
Clock Generator
G
ENERAL
D
ESCRIPTION
The ICS8732I-01 is a low voltage, low skew,
3.3V LVPECL Clock Generator. The ICS8732I-
HiPerClockS™
01 has two selectable clock inputs. The CLK0,
nCLK0 pair can accept most standard differ-
ential input levels. The single ended clock in-
put accepts LVCMOS or LVTTL input levels. The ICS8732I-
01 has a fully integrated PLL along with frequency
configurable outputs. An external feedback input and out-
puts regenerate clocks with “zero delay”.
ICS8732I-01
DATA SHEET
Features
•
Ten differential 3.3V LVPECL output pairs
•
Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL CLK1
inputs
•
CLK0, nCLK0 supports the following input types: LVPECL,
LVDS, LVHSTL, SSTL, HCSL
•
CLK1 accepts the following input levels: LVCMOS or LVTTL
•
Maximum output frequency: 350MHz
•
VCO range: 250MHz to 700MHz
•
External feedback for “zero delay” clock regeneration with
configurable frequencies
•
Cycle-to-cycle jitter: CLK0, nCLK0, 50ps (maximum),
CLK1, 80ps (maximum)
•
Output skew: 75ps (maximum)
•
Static phase offset: -100ps to 200ps
•
Full 3.3V supply mode
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
The ICS8732I-01 has multiple divide select pins for each
bank of outputs along with 3 independent feedback divide
select pins allowing the ICS8732I-01 to function both as a
frequency multiplier and divider. The PLL_SEL input can
be used to bypass the PLL for test and system debug pur-
poses. In bypass mode, the input clock is routed around
the PLL and into the internal output dividers.
B
LOCK
D
IAGRAM
CLK_SEL
P
IN
A
SSIGNMENT
FBDIV_SEL2
FBDIV_SEL1
FBDIV_SEL0
nFB_IN
nQFB0
nQFB1
FB_IN
QFB0
QFB1
V
CCO
V
CC
V
EE
V
EE
CLK0
nCLK0
CLK1
FB_IN
nFB_IN
0
1
0
PLL
1
÷2 ÷4 ÷6 ÷8
÷2 ÷4 ÷8 ÷12
÷4 ÷6 ÷8 ÷10
÷8 ÷12 ÷16 ÷20
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
QFB0
nQFB0
QFB1
nQFB1
V
CCO
QA0
nQA0
QA1
nQA1
V
EE
PLL_SEL
V
CCO
QA2
nQA2
QA3
nQA3
V
EE
1
2
3
4
5
6
7
8
9
52 51 50 49 48 47 46 45 44 43 42 41 40
39
38
37
36
35
34
V
CCO
nQB3
QB3
nQB2
QB2
V
EE
MR
V
CCO
nQB1
QB1
nQB0
QB0
V
EE
PLL_SEL
DIV_SELA0
DIV_SELA1
DIV_SELB0
DIV_SELB1
FBDIV_SEL0
FBDIV_SEL1
FBDIV_SEL2
ICS8732I-01
33
32
31
30
29
28
10
11
12
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
DIV_SELA1
DIV_SELA0
V
CC
V
EE
CLK1
nCLK0
CLK0
CLK_SEL
V
CCA
nc
DIV_SELB1
DIV_SELB0
V
CC
MR
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
1
©2009
Integrated Device Technology, Inc.
ICS8732AYI-01 REVISION A NOVEMBER 10, 2009
ICS8732I-01 Data Sheet
LOW VOLTAGE, LOW SKEW, 3.3V LVPECL CLOCK GENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 8, 32, 39, 40
2, 3,
4, 5
6, 13, 17, 27,
34, 45, 52
7
9, 10, 1
1, 12
14
15
16, 26, 46
18
19
20
21
22
23
24
25
28, 29,
30, 31
33
35, 36,
37, 38
41, 42,
43, 44
47
48
49
50
51
Name
V
CCO
QA0, nQA0,
QA1, nQA1
V
EE
PLL_SEL
QA2, nQA2,
QA3, nQA3
DIV_SELA1
DIV_SELA0
V
CC
CLK1
nCLK0
CLK0
CLK_SEL
V
CCA
nc
DIV_SELB1
DIV_SELB0
QB0, nQB0,
QB1, nQB1
MR
QB2, nQB2,
QB3, nQB3
QFB1, nQFB1,
QFB0, nQFB0
FB_IN
nFB_IN
FBDIV_SEL0
FBDIV_SEL1
FBDIV_SEL2
Type
Power
Output
Power
Input
Output
Input
Input
Power
Input
Input
Input
Input
Power
Unused
Input
Input
Output
Pulldown
Pullup
Description
Output supply pins.
Differential output pair. LVPECL interface levels.
Negative supply pins.
Selects between the PLL and reference clock as the input to the dividers.
When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS / LVTTL interface levels.
Differential output pairs. LVPECL interface levels.
Determines output divider valued in Table 3.
LVCMOS / LVTTL interface levels.
Determines output divider valued in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
Core supply pins.
Pulldown LVCMOS / LVTTL reference clock input.
Pullup
Inver ting differential clock input.
Pulldown Non-inver ting differential clock input.
Clock select input. When LOW, selects CLK0, nCLK0.
Pulldown
When HIGH, selects CLK1. LVCMOS / LVTTL interface levels.
Analog supply pin.
No connect.
Determines output divider valued in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
Determines output divider valued in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
Differential output pairs. LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs Qx to go low and the inver ted outputs
Pulldown
nQx to go high. When LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
Differential output pairs. LVPECL interface levels.
Differential feedback output pairs. LVPECL interface levels.
Feedback input to phase detector for regenerating clocks
with "zero delay".
Feedback input to phase detector for regenerating clocks
Pullup
with "zero delay".
Selects divide value for differential feedback output pairs.
Pulldown
LVCMOS / LVTTL interface levels.
Selects divide value for differential feedback output pairs.
Pulldown
LVCMOS / LVTTL interface levels.
Selects divide value for differential feedback output pairs.
Pulldown
LVCMOS / LVTTL interface levels.
Pulldown
Input
Output
Output
Input
Input
Input
Input
Input
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
ICS8732AYI-01 REVISION A NOVEMBER 10, 2009
2
©2009
Integrated Device Technology, Inc.
ICS8732I-01 Data Sheet
LOW VOLTAGE, LOW SKEW, 3.3V LVPECL CLOCK GENERATOR
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
MR
1
0
0
0
0
0
0
0
0
PLL_SEL
X
1
1
1
1
0
0
0
0
DIV_SELA1
X
0
0
1
1
0
0
1
1
FOR
QA0:QA3 O
UTPUTS
Outputs
QA0:QA3, nQA0:nQA3
Low
fVCO/2
fVCO/4
fVCO/6
fVCO/8
fREF_CLK/2
fREF_CLK/4
fREF_CLK/6
fREF_CLK/8
DIV_SELA0
X
0
1
0
1
0
1
0
1
T
ABLE
3B. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
MR
1
0
0
0
0
0
0
0
0
PLL_SEL
X
1
1
1
1
0
0
0
0
DIV_SELB1
X
0
0
1
1
0
0
1
1
FOR
QB0:QB3 O
UTPUTS
Outputs
QB0:QB3, nQB0:nQB3
Low
fVCO/2
fVCO/4
fVCO/8
fVCO/12
fREF_CLK/2
fREF_CLK/4
fREF_CLK/8
fREF_CLK/12
DIV_SELB0
X
0
1
0
1
0
1
0
1
ICS8732AYI-01 REVISION A NOVEMBER 10, 2009
3
©2009
Integrated Device Technology, Inc.
ICS8732I-01 Data Sheet
LOW VOLTAGE, LOW SKEW, 3.3V LVPECL CLOCK GENERATOR
T
ABLE
3C. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE FOR
QFB0, QFB1
Inputs
MR
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PLL_SEL
X
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
FBDIV_SEL2
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FBDIV_SEL1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FBDIV_SEL0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Outputs
QFB0, QFB1
nQFB0, nQFB1
Low
fVCO/4
fVCO/6
fVCO/8
fVCO/10
fVCO/8
fVCO/12
fVCO/16
fVCO/20
fREF_CLK/4
fREF_CLK/6
fREF_CLK/8
fREF_CLK/10
fREF_CLK/8
fREF_CLK/12
fREF_CLK/16
fREF_CLK/20
T
ABLE
3D. Q
X
O
UTPUT
F
REQUENCY W
/FB_IN = QFB0
OR
QFB1
Inputs
FB_IN
QFB
QFB
QFB
QFB
QFB
QFB
QFB
QFB
FBDIV_SEL2
0
0
0
0
1
1
1
1
FBDIV_SEL1
0
0
1
1
0
0
1
1
FBDIV_SEL0
0
1
0
1
0
1
0
1
Output Divider Mode
÷4
÷6
÷8
÷
10
÷8
÷
12
÷
16
÷
20
CLK1 (MHz)
Minimum
62.5
41.67
31.25
25
31.25
20.83
15.62
12.5
Maximum
175
(NOTE 1)
116.67
87.5
70
87.5
58.33
43.75
35
fVCO
fREF_CLK x 4
fREF_CLK x 6
fREF_CLK x 8
fREF_CLK x 10
fREF_CLK x 8
fREF_CLK x 12
fREF_CLK x 16
fREF_CLK x 20
(NOTE 2)
NOTE 1: The maximum input frequency that the phase detector can accept is 175MHz.
NOTE 2: VCO frequency range is 250MHz to 600MHz for fREF_CLK x 20.
ICS8732AYI-01 REVISION A NOVEMBER 10, 2009
4
©2009
Integrated Device Technology, Inc.
ICS8732I-01 Data Sheet
LOW VOLTAGE, LOW SKEW, 3.3V LVPECL CLOCK GENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5 V
50mA
100mA
42.3°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol Parameter
V
CC
V
CCA
V
CCO
I
CC
I
CCA
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
165
15
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
V
IH
V
IL
I
IH
Input High Voltage
Input Low Voltage
CLK_SEL, MR, CLK1
DIV_SELAx, DIV_SELBx,
FBDIV_SELx
PLL_SEL
CLK_SEL, MR, CLK1
DIV_SELAx, DIV_SELBx,
FBDIV_SELx
PLL_SEL
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
Input High Current
I
IL
Input Low Current
ICS8732AYI-01 REVISION A NOVEMBER 10, 2009
5
©2009
Integrated Device Technology, Inc.
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
