D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
SN74BCT29854
8 BIT TO 9 BIT PARITY BUS TRANSCEIVER
SCBS257 − SEPTEMBER 1987 − REVISED NOVEMBER 1993
•
•
•
•
•
•
•
•
BiCMOS Process With TTL Inputs and
Outputs
State-of-the-Art BiCMOS Design
Significantly Reduces Standby Current
Flow-Through Pinout (All Inputs on
Opposite Side From Outputs)
Functionally Equivalent to AMD Am29854
High-Speed Bus Transceiver With Parity
Generator/ Checker
Parity-Error Flag With Open-Collector
Output
Latch for Storage of the Parity-Error Flag
Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
DW OR NT PACKAGE
(TOP VIEW)
OEA
A1
A2
A3
A4
A5
A6
A7
A8
ERR
CLR
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
B1
B2
B3
B4
B5
B6
B7
B8
PARITY
OEB
LE
description
The SN74BCT29854 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between
data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted
from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not
an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device
so that the buses are effectively isolated.
A 9-bit parity generator/ checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports
with an open-collector parity-error (ERR) flag. ERR can be either passed, sampled, stored, or cleared from the
latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is
transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition
which gives the designer more system diagnostic capability. The SN74BCT29854 provides inverting logic.
The SN74BCT29854 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OEB
L
H
H
X
OEA
H
L
L
X
CLR
X
X
H
L
H
L
X
X
X
LE
X
L
H
H
H
H
L
L
X
Ai
∑
of H’s
Odd
Even
NA
NA
X
X
X
L Odd
H Even
Odd
Even
Bi†
∑
of L’s
NA
Odd
Even
X
X
A
NA
B
X
X
OUTPUT AND I/O
B
A
NA
NA
NA
PARITY
H
L
NA
NA
NA
ERR‡
NA
H
L
N−1
H
NC
H
L
H
NA
FUNCTION
A data to B bus and generate parity
B data to A bus and check parity
Store error flag
Clear error-flag register
Isolation§
H
H
X
Z
Z
Z
L
L
NA
NA
A
L
H
A data to B bus and generate inverted
parity
NA = not applicable, NC = no change, X = don’t care
† Summation of low-level inputs includes PARITY along with Bi inputs.
‡ Output states shown assume the ERR output was previously high.
§ In this mode, the ERR output, when enabled, shows noninverted parity of the A bus.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1993, Texas Instruments Incorporated
POST OFFICE BOX 655303
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251−1443
•
DALLAS, TEXAS 75265
2−1
SN74BCT29854
8 BIT TO 9 BIT PARITY BUS TRANSCEIVER
SCBS257 − SEPTEMBER 1987 − REVISED NOVEMBER 1993
logic diagram (positive logic)
8
EN
8x
8
8x
8
B1 −B8
A1 −A8
EN
OEB
OEA
8
PARITY
8
MUX
1
1
1
1
G1
LE
CLR
ERR
9
2k
P
2−2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
SN74BCT29854
8 BIT TO 9 BIT PARITY BUS TRANSCEIVER
SCBS257 − SEPTEMBER 1987 − REVISED NOVEMBER 1993
error-flag waveforms
OEB
H
L
H
L
OEA
Bi + PARITY
Even
Odd
LE
H
L
CLR
H
L
ERR
Pass
Store
Clear
ERROR-FLAG FUNCTION TABLE
INPUTS
LE
L
CLR
L
INTERNAL
TO DEVICE
POINT P
L
H
L
X
H
X
X
OUTPUT
PRESTATE
ERRn−1†
X
X
L
H
X
L
H
OUTPUT
FUNCTION
ERR
L
H
L
L
H
H
L
H
Pass
Sample
H
L
L
H
H
H
L
H
Sample
Clear
Store
† ERRn−1 represents the state of the ERR output before any changes at CLR, LE,
or point P.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, V
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to a disabled I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
2−3
SN74BCT29854
8 BIT TO 9 BIT PARITY BUS TRANSCEIVER
SCBS257 − SEPTEMBER 1987 − REVISED NOVEMBER 1993
recommended operating conditions
MIN
VCC
VIH
VIL
VOH
IOH
IOL
TA
Supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
High-level output current
Low-level output current
Operating free-air temperature
0
ERR
4.5
2
0.8
2.4
−24
48
70
NOM
5
MAX
5.5
UNIT
V
V
V
V
mA
mA
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
IOH
VOL
II
IIH‡
IIL‡
IOS§
ICCL
Data
Control
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.4 V
VO = 0
Outputs open
−75
55
30
All inputs /outputs except ERR
ERR
VCC = 4.5 V,
VCC = 4.5 V
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
TEST CONDITIONS
II = −18 mA
IOH = − 15 mA
IOH = − 24 mA
VOH = 2.4 V
IOL = 48 mA
VI = 5.5 V
VI = 2.7 V
MIN
2.4
2
20
0.35
0.5
0.1
20
−0.2
−0.75
−250
80
45
mA
mA
mA
mA
V
µA
V
mA
µA
TYP†
MAX
−1.2
UNIT
V
ICCZ
VCC = 5.5 V,
Outputs open
† All typical values are at VCC = 5 V, TA = 25°C.
‡ These parameters include off-state output current for I/O ports only.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
MIN
LE low
tw
tsu
th
Pulse duration
Setup time before LE↓
Hold time after LE↓
CLR low
Bi and PARITY
Bi and PARITY
10
10
18
8
ns
ns
ns
MAX
UNIT
2−4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
