32bit TX System RISC
TX19 family
TMP1942CYUE
TMP1942CZUE/XBG
Rev1.0
March 29, 2007
TX1942CY/CZ
32-Bit RISC Microprocessor TX19 Family
TMP1942CYUE/CZUE/CZXBG
1.
Outline and Features
The TX19 is a family of high-performance 32-bit microprocessors that offers the speed of a 32-bit RISC
solution with the added advantage of a significantly reduce code size of a 16-bit architecture. The instruction set
of the TX19 includes as a subset the 32-bit instructions of the TX39, which is based on the MIPS R3000A
TM
architecture. Additionally, the TX19 supports the MIPS16
TM
Application-Specific Extensions (ASE) for
improved code density.
The TMP1942 is built on a TX19 core processor and a selection of intelligent peripherals. The TMP1942 is
suitable for low-voltage, low-power applications.
Features of the TMP1942 include the following:
RESTRICTIONS ON PRODUCT USE
070122EBP
•
The information contained herein is subject to change without notice.
021023_D
•
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making
a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA
products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set
forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions
set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.
021023_A
•
The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer,
personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These
TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality
and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”).
Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation
instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices,
etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk.
021023_B
•
The products described in this document shall not be used or embedded to any downstream products of which
manufacture, use and/or sale are prohibited under any applicable laws and regulations.
060106_Q
•
The information contained herein is presented only as a guide for the applications of our products. No responsibility is
assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use.
No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties.
070122_C
•
The products described in this document are subject to foreign exchange and foreign trade control laws.
060925_E
•
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter
entitled Quality and Reliability Assurance/Handling Precautions.
030619_S
TMP1942CY/CZ-1
TX1942CY/CZ
(1) TX19 core processor
1)
Two instruction set architecture (ISA) modes: 16-bit ISA for code density and 32-bit ISA for speed
•
•
2)
The 16-bit ISA is object-code compatible with the code-efficient MIPS16
TM
ASE.
The 32-bit ISA is object-code compatible with the high-performance TX39 family.
Combines high performance with low power consumption.
-
High performance
•
•
•
•
•
Single clock cycle execution for most instructions
3-operand computational instructions for high instruction throughput
5-stage pipeline
On-chip high-speed memory
DSP function: Executes 32-bit x 32-bit multiplier operations with a 64-bit accumulation in a single
clock cycle.
Optimized design using a low-power cell library
Programmable standby modes in which processor clocks are stopped
Distinct starting locations for each interrupt service routine
Automatically generated vectors for each interrupt source
Automatic updates of the interrupt mask level
-
Low power consumption
•
•
3)
•
•
•
Fast interrupt response suitable for real-time control
(2) Internal RAM: FDUE/FDXBG: 20KB,CYUE/CZUE/CZXBG: 16 KB
Internal ROM: FDUE/FDXBG: 512KB,CYUE/CZXBG: 384KB,CYUE: 256 KB
ROM correction function (8 words x 4 blocks)
(For FDUE/FDXBG, only registers are available; data is not replaced.)
(3) External memory expansion
•
•
•
16-Mbyte off-chip address space for code and data
External bus interface with dynamic bus sizing for 8-bit and 16-bit data ports
(4) 4-channel DMA controller
Interrupt- or software-triggered
(5) 6 channel 8-bit PWM timer
(12 channel 8-bit interval timer, 6 channel 16-bit interval timer, 6 channel 8-bit PPG output)
(6) 14 channel 16-bit timer
(2 channels support 2-phase input pulse counter mode.)
(7) 1 channel real-time counter (RTC)
(8) 5 channel general-purpose serial interface
(Supports both UART and synchronous transfer modes)
(9) 1 channel serial bus interface
Either I
2
C bus mode or clock-synchronous mode can be selected.
(10) 16 channel 10-bit A/D converter (with internal sample/hold)
Conversion time: 2
µs
(throughput), 4 to 5
µs
(latency)
(11) 3 channel 10-bit D/A converter
(12) Watchdog timer
(13) 4 channel chip select/wait controller
TMP1942CY/CZ-2
TX1942CY/CZ
(14) Interrupt sources
•
•
•
4 CPU interrupts:
software interrupt instruction
45 internal interrupts: 7 priority levels, with the exception of the watchdog timer interrupt
29 external interrupts: 7 priority levels, with the exception of the NMI interrupt
The external sources include 14 KWUP sources, which are all assigned to a
single interrupt vector, and 4 extended interrupts (INTB, INTC, INTD, and
INTE), which are all assigned to a single interrupt vector with an identification
flag. Thus, the actual number of external interrupt sources is 13.
(15) 108 pin input/output ports
(16) Three standby function
•
•
•
•
IDLE, SLEEP, and STOP
(17) Dual clocks
RTC clock: Low-speed clock (32.768 kHz)
(18) Clock generator
On-chip PLL (x4)
Clock gear: Divides the operating speed of the CPU by 1/2, 1/4 or 1/8
(19) Operating voltage range: 2.7 to 3.6 V
PC and PF are 2.7 to 3.6 V or 4.5 to 5.25 V for 5 V-enabled ports.
(20) Operating frequency
•
•
•
•
32 MHz (Vcc
≥
3.0 V)
28 MHz (Vcc
≥
2.7 V)
(21) Package
144-pin QFP (16 x 16 x 1.4 (t) mm, 0.4-mm pitch): FDUE/CZUE/CYUE
177-pin CSP (13 x 13 x 1.4 (t) mm, 0.8-mm pitch): FDXBG/CZXBG
Note: TMP1942FDXBG (Package: 177-pin CSP) is under development.
TMP1942CY/CZ-3
TX1942CY/CZ
TX19 Proccessor Core
TX19 CPU
(*) MROM for the mask ROM
version.
CZUE/XBG:384KB
MAC
DSU
256 KBROM
(*)
16 KBRAM
ROM correction
DMAC (4ch)
NMI
INT0 (PF6)
INT1∼2 (PE6∼7)
INT3∼4 (PA0∼1)
INT5∼6 (PA3∼4)
INT7 (PB7)
INT8∼A (PC0∼2)
AN0∼7 (P50∼57)
AN8∼15 (P60∼67)
ADTRG (P57)
AVCC/AVSS
VREFH/VREFL
CG
G-Bus
X1
X2
XT1 (PD6)
XT2 (PD7)
SCOUT (P44)
PLLOFF*
INTC
EBIF
RESET*
I/O Bus I/F
10-bit
ADC (16ch)
BW0/1
INTLV (PE7)
DAOUT0∼3
DAVCC/DAVSS
DAREFH
10-bit
DAC (3ch)
PORT0
AD0∼7 (P00∼P07)
TXD0 (PD0)
RXD0 (PD1)
SCLK0/CTS0 (PD2)
PORT1
SIO0
PORT2
AD8/A8∼AD15/A15 (P10∼P17)
A0/A16∼A7/A23 (P20∼P27)
TXD1 (PD3)
RXD1 (PD4)
SCLK1/CTS1 (PD5)
RD (P30)
TXD3 (PE0)
RXD3 (PE1)
SCLK3/CTS3 (PE2)
SCK (PF3)
SO/SDA (PF4)
SI/SCL (PF5)
TXD4 (PE3)
RXD4 (PE4)
SCLK4/CTS4 (PE5)
TXD5 (PF0)
RXD5 (PF1)
SCLK5/CTS5 (PF2)
TB4IN1 (PB5),
TB0IN0∼1 (PA0∼1)
TB7IN0∼1 (P95∼96), TB1IN0∼1 (PA3∼4)
TB8IN0∼1 (PC6∼7), TB2IN0∼1 (PB0∼1)
TB9IN0∼1 (PD0∼1), TB3IN0∼1 (PB3∼4)
TBAIN0∼1 (PD5∼6),
TB4IN0 (PB2)
TB0OUT (PA2),
TB1OUT (PA5),
TB2OUT (PB2),
TB3OUT (PB5),
TB4OUT (P92)
TB5OUT (P93)
TB6OUT (P94)
TB7OUT (P97)
WR (P31)
SIO1
SIO3
PORT3
SERIAL
BUS I/F
HWR (P32)
WAIT (P33)
BUSRD (P34)
BUSAK* (P35)
R/W (P36)
P37
SIO4
PORT4
SIO5
WDT
CS0∼CS3 (P40∼P43)
16-bit TMR0-D
(14ch)
Real-Time
Counter (RTC)
INTB∼C (PB0∼1)
INTBCDE
8-bit TMR0/1
∼
A/B
(12ch)
INTD∼E (PB3∼4)
TA1OUT (PA6), TA7OUT (PC5)
TA3OUT (PB6), TA9OUT (PC7)
TA5OUT (PC3), TABOUT (PD5)
TA0IN (PA7),
TA2IN (PB7),
TA4IN (PC0),
TA6IN (PC1)
TA8IN (PC2)
TAAIN (PC4)
KWUP
JTAG
Figure 1.1 TMP1942 Block Diagram
TMP1942CY/CZ-4
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