supports static lane reversal. For example, lane reversal for upstream
port A may be configured by asserting the PCI Express Port A Lane
Reverse (PEALREV) input signal or through serial EEPROM or SMBus
initialization. Lane reversal for port C may be enabled via a configura-
tion space register, serial EEPROM, or the SMBus.
Product Description
Utilizing standard PCI Express interconnect, the PES8NT2 provides
the most efficient high-performance I/O connectivity solution for applica-
tions requiring high throughput, low latency, and simple board layout
with a minimum number of board layers. With support for non-trans-
parent bridging, the PES8NT2 is part of the IDT PCIe System Intercon-
nect Products that target multi-host and intelligent I/O applications
requiring inter-domain communication. The PES8NT2 provides 32 Gbps
(4 GBps) of aggregated, full-duplex switching capacity through 8 inte-
grated serial lanes, using proven and robust IDT technology. Each lane
provides 2.5 Gbps of bandwidth in both directions and is fully compliant
with PCI Express Base specification 1.0a.
The PES8NT2 is based on a flexible and efficient layered architec-
ture. The PCI Express layer consists of SerDes, Physical, Data Link,
and Transaction layers in compliance with PCI Express Base specifica-
tion Revision 1.0a. The PES8NT2 can operate either as a store and
forward or cut-through switch depending on the packet size and is
designed to switch memory and I/O transactions. It supports eight Traffic
Classes (TCs) and one Virtual Channel (VC) with sophisticated resource
management.
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January 5, 2009
IDT 89HPES8NT2 Data Sheet
CPU
PES8NT2
CPU
PES8NT2
CPU
PES8NT2
PCIe System Interconnect Switch
Embedded
CPU
Embedded
CPU
SATA / SAS
Embedded
CPU
GbE / 10GigE
FC
Figure 2 PCIe System Interconnect Architecture Block Diagram
Pin Description
The following tables list the functions of the pins provided on the PES8NT2. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
PEALREV
Type
I
Name/Description
PCI Express Port A Lane Reverse.
When this bit is asserted, the lanes of
PCI Express Port A are reversed. This value may be overridden by modify-
ing the value of the PALREV bit in the PA_SWCTL register.
PCI Express Port A Serial Data Receive.
Differential PCI Express receive
pairs for port A.
PCI Express Port A Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port A
PCI Express Port C Lane Reverse.
When this bit is asserted, the lanes of
PCI Express Port C are reversed. This value may be overridden by modify-
ing the value of the PCLREV bit in the PA_SWCTL register.
PCI Express Port C Serial Data Receive.
Differential PCI Express receive
pairs for port C.
PCI Express Port C Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port C
PCI Express Reference Clock.
Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
PCI Express Reference Clock Mode Select.
These signals select the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 1 PCI Express Interface Pins
PEARP[3:0]
PEARN[3:0]
PEATP[3:0]
PEATN[3:0]
PECLREV
I
O
I
PECRP[3:0]
PECRN[3:0]
PECTP[3:0]
PECTN[3:0]
PEREFCLKP[1:0]
PEREFCLKN[1:0]
I
O
I
REFCLKM
I
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January 5, 2009
IDT 89HPES8NT2 Data Sheet
Signal
MSMBADDR[4:1]
MSMBCLK
Type
I
I/O
Name/Description
Master SMBus Address.
These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
Master SMBus Clock.
This bidirectional signal is used to synchronize
transfers on the master SMBus. It is active and generating the clock only
when the EEPROM is being accessed.
Master SMBus Data.
This bidirectional signal is used for data on the mas-
ter SMBus.
Slave SMBus Address.
These pins determine the SMBus address to
which the slave SMBus interface responds.
Slave SMBus Clock.
This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
Slave SMBus Data.
This bidirectional signal is used for data on the slave
SMBus.
Table 2 SMBus Interface Pins
MSMBDAT
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
I/O
I
I/O
I/O
Signal
GPIO[0]
GPIO[1]
Type
I/O
I/O
Name/Description
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PECRSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port C
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PALINKUPN
Alternate function pin type: Output
Alternate function: Port A link up status output
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PCLINKUPN
Alternate function pin type: Output
Alternate function: Port C link up status output
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: FAILOVERP
Alternate function pin type: Input
Alternate function: NTB upstream port failover
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Table 3 General Purpose I/O Pins
GPIO[2]
I/O
GPIO[3]
GPIO[4]
I/O
I/O
GPIO[5]
I/O
GPIO[6]
GPIO[7]
I/O
I/O
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January 5, 2009
IDT 89HPES8NT2 Data Sheet
Signal
CCLKDS
Type
I
Name/Description
Common Clock Downstream.
When the CCLKDS pin is asserted, it indi-
cates that a common clock is being used between the downstream device
and the downstream port.
Common Clock Upstream.
When the CCLKUS pin is asserted, it indi-
cates that a common clock is being used between the upstream device and
the upstream port.
Master SMBus Slow Mode.
The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 KHz. This value
may not be overridden.
Non-Transparent Bridge Reset.
Assertion of this signal indicates a reset
on the external side of the non-transparent bridge. This signal is only used
when the switch mode selects a non-transparent mode and has no effect
otherwise.
Fundamental Reset.
Assertion of this signal resets all logic inside the
PES8NT2 and initiates a PCI Express fundamental reset.
Reset Halt.
When this signal is asserted during a PCI Express fundamental
reset, the PES8NT2 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the PA_SWCTL register by an SMBus master.
Switch Mode.
These configuration pins determine the PES8NT2 switch
operating mode.
0x0 - Transparent mode
0x1 -Transparent mode with serial EEPROM initialization
0x2 - Non-transparent mode
0x3 - Non-transparent mode with serial EEPROM initialization
0x4 - Non-transparent failover mode
0x5 - Non-transparent failover mode with serial EEPROM initialization
0x6 through 0xF - Reserved
Table 4 System Pins
CCLKUS
I
MSMBSMODE
I
PENTBRSTN
I
PERSTN
RSTHALT
I
I
SWMODE[3:0]
I
Signal
JTAG_TCK
Type
I
Name/Description
JTAG Clock.
This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG Data Input.
This is the serial data input to the boundary scan logic or
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