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COPYRIGHT © INTEL CORPORATION, 1996
CG-041493
E
1.0
INTRODUCTION
Examining the worst-case timing relations for
interfacing the Intel386™ EX embedded processor
with flash indicates bus contention on a memory read
followed by a memory write. However, the Intel386
EX embedded processor specification t
50
resolves this
issue and guarantees no bus contention if the flash data
float time (t
GHQZ
) is
≤
t
50
. This document explains why
there is no contention when interfacing with Intel
Flash.
AB-66
Using these specifications, a timing analysis shows that
contention occurs when RD# is deasserted late, i.e., 22
ns maximum delay, and D[15:0] is driven early, i.e., 4
ns minimum delay. However spec t
50
guarantees by
design that there is no contention. This is guaranteed
because if RD# goes high late, D[15:0] will also be
driven late as the logic delays of t
10a
and t
12
track each
other across temperature, voltage, and processing
variations. Since t
10a
and t
12
track each other, they are
separated by a CLK2 (each are referenced to a rising
clock edge, separated by a CLK2—20 ns at 25 MHz.).
Therefore, the data float time of the flash memory must
be less than CLK2, as specified by t
50
.
The following example shows the calculation for data
float without using t
50
which yields an unrealistic float
time requirement for flash memory. The example then
shows the correct calculation using the Intel386 EX
embedded processor specification of t
50
.
At 5V V
CC
:
t
10a
= [4, 22] = RD#, WR# Valid Delay
t
12
= [4, 23] = D[15:0] Write Data Valid Delay
t
GHQZ
= Flash Data Float Time (20 ns for
28F400BV)
Analysis without t
50
(incorrect):
t
GHQZ
= CLK2 – t
10a
(max) + t
12
(min)
t
GHQZ
= 20 ns – 22 + 4 = 2 ns.
2.0
READ FOLLOWED BY WRITE
TIMING ANALYSIS
Figure 1 shows the timing for a read followed by a
write, along with the signals that must be evaluated to
determine if bus contention exists. A full timing
diagram is presented in Appendix A. To avoid bus
contention, the flash memory must stop driving “read
data” on the bus before the Intel386 EX embedded
processor starts driving “write data” on the bus.
Controller AC timings are specified with a minimum
and a maximum value. For example, at 5V V
CC
,
25 MHz the RD# valid delay, t
10a
, is specified as 4 ns
minimum and 22 ns maximum. These minimum and
maximum specifications are provided to account for
variations in temperature, voltage, and processing.
0 ns
T2 Read
CLK2
RD# (OE#)
50 ns
100 ns
T1 Write
t
10a
t
GHQZ
t
50
Read Data
150 ns
D[15:0]
t
12
Write Data
2197_01
Figure 1. Interfacing the Intel386™ EX Embedded Processor with Intel Flash
5
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