IDT74LVCH16260A
3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 12-BIT
TRI-PORT BUS EXCHANGER
WITH 5 VOLT TOLERANT I/O
AND BUS-HOLD
FEATURES:
Typical
t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.635mm pitch SSOP, 0.50mm pitch TSSOP
and 0.40mm pitch TVSOP packages
– Extended commercial range of -40°C to +85°C
– V
CC
= 3.3V ±0.3V, Normal Range
– V
CC
= 2.7V to 3.6V, Extended Range
– CMOS power levels (0.4µ W typ. static)
– All inputs, outputs and I/O are 5 Volt tolerant
– Supports hot insertion
Drive Features for LVCH16260A:
– High Output Drivers: ±24mA
– Reduced system switching noise
–
–
IDT74LVCH16260A
bus multiplexer/transceiver for use in high-speed microprocessor applica-
tions. This bus exchanger supports memory interleaving with latched out-
puts on the B ports and address multiplexing with latched inputs on the B
ports.
The LVCH16260A tri-port bus exchanger has three 12-bit ports. Data
may be transferred between the A port and either/both of the B ports. The
latch enable (LE1B, LE2B, LEA1B and LEA2B) inputs control data storage.
When a latch-enable input is high, the latch is transparent. When a latch-
enable input is low, the data at the input is latched and remains latched until
the latch enable input is returned high. Independent output enables (OE1B
and
OE2B)
allow reading from one port while writing to the other port.
All pins of the 12-bit Bus Exchanger can be driven from either 3.3V or
5V devices. This feature allows the use of the device as a translator in a
mixed 3.3V/5V supply system.
The LVCH16260A has been designed with a ±24mA output driver. The
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16260A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DESCRIPTION:
The LVCH16260A tri-port bus exchanger is built using advanced dual
metal CMOS technology. The LVCH16260A is a high-speed 12-bit latched
Functional Block Diagram
OE1B
29
LEA1B
30
A-1B
LATCH
12
1B
1:12
LE1B
2
12
28
1
1B-A
LATCH
12
12
SEL
OEA
A
1:12
12
M
U
X
1
0
12
27
12
LE2B
2B-A
LATCH
12
55
LEA2B
56
A-2B
LATCH
2B
1:12
12
OE2B
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4229/1
IDT74LVCH16260A
3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
OEA
LE1B
2B
3
GND
2B
2
2B
1
V
CC
A
1
A
2
A
3
GND
A
4
A
5
A
6
A
7
A
8
A
9
GND
A
10
A
11
A
12
V
CC
1B
1
1B
2
GND
1B
3
LE2B
SEL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
SO56-1
SO56-2 43
SO56-3
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OE2B
LEA2B
2B
4
GND
2B
5
2B
6
V
CC
2B
7
2B
8
2B
9
GND
2B
10
2B
11
2B
12
1B
12
1B
11
1B
10
GND
1B
9
1B
8
1B
7
V
CC
1B
6
1B
5
GND
1B
4
LEA1B
OE1B
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through
each V
CC
or GND
(1)
Unit
V
V
°C
mA
mA
mA
LVC Link
Max.
– 0.5 to +6.5
– 0.5 to +6.5
– 65 to +150
– 50 to +50
– 50
±100
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
6.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
LVC Link
NOTE:
1. As applicable to the device type.
SSOP/ TSSOP/ TVSOP
TOP VIEW
c
1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74LVCH16260A
3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
FUNCTION TABLES
1Bx
H
L
X
X
X
X
X
2Bx
X
X
X
H
L
X
X
Inputs
SEL
LE1B
H
H
H
L
L
L
X
H
H
L
X
X
X
X
(1)
Outputs
Ax
H
L
A
0
(2)
H
L
A
0
(2)
Z
Inputs
Ax
H
L
H
L
H
L
X
X
X
X
X
LEA1B LEA2B
H
H
H
H
L
L
L
X
X
X
X
H
H
L
L
H
H
L
X
X
X
X
OE1B
L
L
L
L
L
L
L
H
L
H
L
OE2B
L
L
L
L
L
L
L
H
H
L
L
1Bx
H
L
H
L
B
0
(2)
B
0
(2)
B
0
(2)
Z
Active
Z
Active
Outputs
2Bx
H
L
B
0
(2)
B
0
(2)
H
L
B
0
(2)
Z
Z
Active
Active
LE2B
X
X
X
H
H
L
X
OEA
L
L
L
L
L
L
H
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
2. A
0
, B
0
= Output level before the indicated steady-state input
conditions were established.
PIN DESCRIPTION
Signal
A
(1:12)
1B
(1:12)
2B
(1:12)
LEA1B
LEA2B
LE1B
LE2B
SEL
OEA
OE1B
OE2B
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
Description
Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.
(1)
Bidirectional Data Port 1B. Connected to the even path or even bank of memory.
(1)
Bidirectional Data Port 2B. Connected to the odd path or odd bank of memory.
(1)
Latch Enable Input for A-1B Latch. The Latch is open when LEA1B is HIGH. Data from the A-port is latched on the HIGH to LOW
transition of LEA1B.
Latch Enable Input for A-2B Latch. The Latch is open when LEA2B is HIGH. Data from the A-port is latched on the HIGH to LOW
transition of LEA2B.
Latch Enable Input for 1B-A Latch. The Latch is open when LE1B is HIGH. Data from the 1B port is latched on the HIGH to LOW
transition of LE1B.
Latch Enable Input for 2B-A Latch. The Latch is open when LE2B is HIGH. Data from the 2B port is latched on the HIGH to LOW
transition of LE2B.
1B or 2B Path Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL enables data transfer
from 2B Port to A Port.
Output Enable for A Port (Active LOW).
Output Enable for 1B Port (Active LOW).
Output Enable for 2B Port (Active LOW).
NOTE:
1. These pins have “Bus-hold”. All other pins are standard inputs, outputs, or I/Os.
3
IDT74LVCH16260A
3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40
O
C to +85
O
C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
OFF
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input Leakage Current
High Impedance Output Current
(3-State Output pins)
Input/Output Power Off Leakage
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 0V, V
IN
or V
O
≤
5.5V
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
3.6
≤
V
IN
≤
5.5V
(2)
Quiescent Power Supply
Current Variation
One input at V
CC
- 0.6V
other inputs at V
CC
or GND
—
—
—
—
—
—
—
– 0.7
100
—
—
—
±50
– 1.2
—
10
10
500
µA
LVC Link
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= 0 to 5.5V
V
O
= 0 to 5.5V
Min.
1.7
2
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
Max.
—
—
0.7
0.8
±5
±10
Unit
V
V
µA
µA
µA
V
mV
µA
NOTES:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
2. This applies in the disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
LVC Link
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3.0V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2.0V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
—
—
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
± 500
Unit
µA
µA
µA
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
4
IDT74LVCH16260A
3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
2.2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
LVC Link
Unit
V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to +85°C.
OPERATING CHARACTERISTICS, VCC = 3.3V
±
0.3V, TA = 25°C
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance per bus exchanger Outputs enabled
Power Dissipation Capacitance per bus exchanger Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
Unit
pF
pF
SWITCHING CHARACTERISTICS
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
t
SK
(o)
Parameter
Propagation Delay
A
X
to 1B
X
or Ax to 2B
X
Propagation Delay
1B
X
to A
X
or 2B
X
to A
X
Propagation Delay
LE
X
B to A
X
Propagation Delay
LEA1B to 1B
X
or LEA2B to 2B
X
Propagation Delay
SEL to A
X
Output Enable Time
OEA
to A
X
,
OE1B
to 1B
X,
or
OE2B
to 2B
X
Output Disable Time
OEA
to A
X
,
OE1B
to 1B
X,
or
OE2B
to 2B
X
Set-Up Time, HIGH or LOW Data to Latch
Hold Time, Latch to Data
Pulse Width, Latch HIGH
Output Skew
(2)
(1)
V
CC
= 2.7V±0.2V
Min.
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1
1.2
3
—
Max.
5.7
6.1
6.1
6.1
6.3
6.7
5.9
—
—
—
—
Min.
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1
1
3
—
V
CC
= 3.3V±0.3V
Max.
5
5.2
5.2
5
5.2
5.5
5.2
—
—
—
500
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
NOTES:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
5
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