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74AC11374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS214A − JULY 1987 − REVISED APRIL 1996
D
D
D
D
D
D
D
D
Eight D-Type Flip-Flops in a Single Package
3-State Bus-Driving True Outputs
Full Parallel Access for Loading
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPICt
(Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, and Standard
Plastic 300-mil DIPs (NT)
DB, DW, OR NT PACKAGE
(TOP VIEW)
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
1D
2D
3D
4D
V
CC
V
CC
5D
6D
7D
8D
CLK
description
This 8-bit flip-flop features 3-state outputs designed specifically for driving highly-capacitive or relatively
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The eight flip-flops of the 74AC11374 are edge-triggered D-type flip-flops. On the positive transition of the clock,
the Q outputs are set to the logic levels set up at the D inputs.
The output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low
logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines signigicantly. The high-impedance third state provides the capability to drive the bus lines in a
bus-organized system without need for interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The 74AC11374 is characterized for operation from −40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
L
L
L
L
L
H
CLK
↑
↑
L
H
↓
X
D
H
L
X
X
X
X
OUTPUT
Q
H
L
Q
0
Q
0
Q
0
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1996, Texas Instruments Incorporated
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1
74AC11374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS214A − JULY 1987 − REVISED APRIL 1996
logic symbol
†
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
†
24
13
23
22
21
20
17
16
15
14
EN
C1
1D
1
2
3
4
9
10
11
12
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE
CLK
24
13
1D
23
C1
1D
1
1Q
2D
22
C1
1D
2
2Q
3D
21
C1
1D
3
3Q
4D
20
C1
1D
4
4Q
5D
17
C1
1D
9
5Q
6D
16
C1
1D
10
6Q
7D
15
C1
1D
11
7Q
8D
14
C1
1D
12
8Q
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
74AC11374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS214A − JULY 1987 − REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±200
mA
Maximum power dissipation at T
A
= 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . 0.65 W
DW package . . . . . . . . . . . . . . . . . . 1.7 W
NT package . . . . . . . . . . . . . . . . . . . 1.3 W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils,
except for the NT package, which has a trace length of zero.
†
recommended operating conditions
MIN
V
CC
V
IH
Supply voltage
V
CC
= 3 V
High level
High-level input voltage
V
CC
= 4.5 V
V
CC
= 5.5 V
V
CC
= 3 V
V
IL
V
I
V
O
I
OH
Low level
Low-level input voltage
Input voltage
Output voltage
V
CC
= 3 V
High level
High-level output current
V
CC
= 4.5 V
V
CC
= 5.5 V
V
CC
= 3 V
I
OL
Low level
Low-level output current
V
CC
= 4.5 V
V
CC
= 5.5 V
Dt/Dv
T
A
Data
Input transition rise or fall rate
Operating free-air temperature
OE
0
0
−40
V
CC
= 4.5 V
V
CC
= 5.5 V
0
0
3
2.1
3.15
3.85
0.9
1.35
1.65
V
CC
V
CC
−4
−24
−24
12
24
24
10
5
85
ns/V
°C
mA
mA
V
V
V
V
NOM
5
MAX
5.5
UNIT
V
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
74AC11374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS214A − JULY 1987 − REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
3V
I
OH
= −50
mA
50
V
OH
I
OH
= −4 mA
I
OH
= −24 mA
24
I
OH
= −75 mA
{
I
OL
= 50
mA
V
OL
I
OL
= 12 mA
I
OL
= 24 mA
I
OL
= 75 mA
{
I
OZ
I
I
I
CC
C
i
C
o
†
T
A
= 25°C
MIN
2.9
4.4
5.4
2.58
3.94
4.94
TYP
MAX
MIN
2.9
4.4
5.4
2.48
3.8
4.8
3.85
MAX
UNIT
4.5 V
5.5 V
3V
4.5 V
5.5 V
5.5 V
3V
4.5 V
5.5 V
3V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
I
O
= 0
5.5 V
5V
5V
V
0.1
0.1
0.1
0.36
0.36
0.36
±0.5
±0.1
8
4
10
0.1
0.1
0.1
0.44
0.44
0.44
1.65
±5
±1
80
mA
mA
mA
pF
pF
V
V
O
= V
CC
or GND
V
I
= V
CC
or GND
V
I
= V
CC
or GND,
V
I
= V
CC
or GND
V
O
= V
CC
or GND
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
timing requirements over recommended operating free-air temperature range,
V
CC
= 3.3 V
±
0.3 V (unless otherwise noted) (see Figure 1)
T
A
= 25°C
MIN
f
clock
t
w
t
su
t
h
Clock frequency
Pulse duration
Setup time, data before CLK↑
Hold time, data after CLK↑
CLK low or high
0
6.5
2.5
4.5
MAX
75
MIN
0
6.5
2.5
4.5
MAX
75
UNIT
MHz
ns
ns
ns
timing requirements over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
T
A
= 25°C
MIN
f
clock
t
w
t
su
t
h
Clock frequency
Pulse duration
Setup time, data before CLK↑
Hold time, data after CLK↑
CLK low or high
0
5
2.5
3.5
MAX
95
MIN
0
5
2.5
3.5
MAX
95
UNIT
MHz
ns
ns
ns
4
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