HIGH-SPEED 3.3V
70V3319/99S
256/128K x 18
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
◆
◆
◆
◆
◆
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
– Due to limited pin count PL/
FT
option is not supported
on the 128-pin TQFP package. Device is pipelined
outputs only on each port.
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (6Gbps bandwidth)
– Fast 3.6ns clock to data out
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
◆
◆
◆
◆
◆
◆
◆
◆
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output mode
LVTTL- compatible, single 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 133MHz.
Available in a 128-pin Thin Quad Flatpack, 208-pin fine
pitch Ball Grid Array, and 256-pin Ball
Grid Array
Supports JTAG features compliant to IEEE 1149.1
– Due to limited pin count, JTAG is not supported on the
128-pin TQFP package
Green parts available, see ordering information
Functional Block Diagram
UB
L
LB
L
UB
R
LB
R
FT/PIPE
L
1/0
0a 1a
a
0b 1b
b
1b 0b
b
1a 0a
a
1/0
FT/PIPE
R
R/W
L
CE
0L
CE
1L
1
0
1/0
B
W
0
L
B
W
1
L
B B
WW
1 0
R R
1
0
1/0
R/W
R
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
OE
R
1b 0b 1a 0a
0a 1a 0b 1b
0/1
,
FT/PIPE
R
FT/PIPE
L
0/1
ab
ba
256K x 18
MEMORY
ARRAY
I/O
0L
- I/O
17L
Din_L
Din_R
I/O
0R
- I/O
17R
CLK
L
A
17L(1)
A
0L
REPEAT
L
ADS
L
CNTEN
L
CLK
R
,
A
17R(1)
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0R
REPEAT
R
ADS
R
CNTEN
R
5623 tbl 01
NOTE:
1. A
17
is a NC for IDT70V3399.
TDI
JTAG
TDO
TCK
TMS
TRST
NOVEMBER 2019
DSC
5623/13
1
©2019 Integrated Device Technology, Inc.
70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70V3319/99 is a high-speed 256/128K x 18 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times. With an input data register, the
IDT70V3319/99 has been optimized for applications having unidirectional
or bidirectional data flow in bursts. An automatic power down feature,
controlled by
CE
0
and CE
1,
permits the on-chip circuitry of each port to
enter a very low standby power mode.
The 70V3319/99 can support an operating voltage of either 3.3V or
2.5V on one or both ports, controllable by the OPT pins. The power supply
for the core of the device (V
DD
) remains at 3.3V.
Pin Configuration
(1,2,3,4,5)
1
I/O
9L
2
NC
3
V
SS
4
TDO
5
NC
6
A
16L
7
A
12L
8
A
8L
9
NC
10
V
DD
11
CLK
L
12
CNTEN
L
13
A
4L
14
A
0L
15
OPT
L
16
NC
17
V
SS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
NC
V
SS
NC
TDI
A
17L(1)
A
13L
A
9L
NC
CE
0L
V
SS
ADS
L
A
5L
A
1L
V
SS
V
DDQR
I/O
8L
NC
V
DDQL
I/O
9R
V
DDQR
PIPE/FT
L
NC
A
14L
A
10L
UB
L
CE
1L
V
SS
R/W
L
A
6L
A
2L
V
DD
I/O
8R
NC
V
SS
NC
V
SS
I/O
10L
NC
A
15L
A
11L
A
7L
LB
L
V
DD
OE
L
REPEAT
L
A
3L
V
DD
NC
V
DDQL
I/O
7L
I/O
7R
I/O
11L
NC
V
DDQR
I/O
10R
I/O
6L
NC
V
SS
NC
V
DDQL
I/O
11R
NC
V
SS
V
SS
I/O
6R
NC
V
DDQR
NC
V
SS
I/O
12L
NC
V
DD
NC
V
DDQR
I/O
12R
70V3319/99
BF208
(6)
BFG208
(6)
208-Pin
fpBGA
Top View
(7)
NC
V
DDQL
I/O
5L
NC
V
DD
NC
V
SS
I/O
5R
V
DDQL
V
DD
V
SS
V
SS
V
SS
V
DD
V
SS
V
DDQR
I/O
14R
V
SS
I/O
13R
V
SS
I/O
3R
V
DDQL
I/O
4R
V
SS
NC
I/O
14L
V
DDQR
I/O
13L
NC
I/O
3L
V
SS
I/O
4L
V
DDQL
NC
I/O
15R
V
SS
V
SS
NC
I/O
2R
V
DDQR
NC
V
SS
NC
I/O
15L
I/O
1R
V
DDQL
NC
I/O
2L
I/O
16R
I/O
16L
V
DDQR
NC
TRST
A
16R
A
12R
A
8R
NC
V
DD
CLK
R
CNTEN
R
A
4R
NC
I/O
1L
V
SS
NC
V
SS
NC
I/O
17R
TCK
A
17R(1)
A
13R
A
9R
NC
UB
R
CE
0R
V
SS
ADS
R
A
5R
A
1R
V
SS
V
DDQL
I/O
0R
V
DDQR
NC
I/O
17L
V
DDQL
TMS
NC
A
14R
A
10R
CE
1R
V
SS
R/W
R
A
6R
A
2R
V
SS
NC
V
SS
NC
V
SS
NC
PIPE/FT
R
NC
A
15R
A
11R
A
7R
LB
R
V
DD
OE
R
REPEAT
R
A
3R
A
0R
V
DD
OPT
R
NC
I/O
0L
5623 drw 02c
NOTES:
1. A
17
is a NC for IDT70V3399.
2. All V
DD
pins must be connected to 3.3V power supply.
3. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is
set to V
IL
(0V).
4. All V
SS
pins must be connected to ground supply.
5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
6.42
2
70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration
(1,2,3,4,5)
(con't.)
70V3319/99
BC256
(6)
BCG256
(6)
256-Pin BGA
Top View
(7)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
NC
B1
TDI
B2
NC
B3
A
17L
(1)
A
14L
B4
B5
A
11L
B6
A
8L
B7
NC
B8
CE
1L
B9
OE
L
CNTEN
L
A
5L
B10
B11
B12
A
2L
B13
A
0L
B14
NC
B15
NC
B16
NC
C1
NC
C2
TDO
C3
NC
C4
A
15L
C5
A
12L
C6
A
9L
C7
UB
L
C8
CE
0L
R/W
L
REPEAT
L
C9
C10
C11
A
4L
C12
A
1L
C13
V
DD
C14
NC
C15
NC
C16
NC
D1
I/O
9L
D2
V
SS
D3
A
16L
D4
A
13L
D5
A
10L
D6
A
7L
D7
NC
D8
LB
L
D9
CLK
L
ADS
L
D10
D11
A
6L
D12
A
3L
D13
OPT
L
D14
NC
D15
I/O
8L
D16
NC
E1
I/O
9R
E2
NC
E3
PIPE/FT
L
V
DDQL
E4
E5
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DD
E6
E7
E8
E9
E10
E11
E12
E13
NC
E14
NC
E15
I/O
8R
E16
I/O
10R
I/O
10L
F1
F2
NC
F3
V
DDQL
F4
V
DD
F5
V
DD
F6
V
SS
F7
V
SS
F8
V
SS
F9
V
SS
F10
V
DD
F11
V
DD
V
DDQR
F12
F13
NC
F14
I/O
7L
I/O
7R
F15
F16
I/O
11L
G1
NC
G2
I/O
11R
V
DDQL
V
DD
G3
G4
G5
V
SS
G6
V
SS
G7
V
SS
G8
V
SS
G9
V
SS
G10
V
SS
G11
V
DD
V
DDQR
I/O
6R
G12
G13
G14
NC
G15
I/O
6L
G16
NC
H1
NC
H2
I/O
12L
V
DDQR
H3
H4
V
SS
H5
V
SS
H6
V
SS
H7
V
SS
H8
V
SS
H9
V
SS
H10
V
SS
H11
V
SS
H12
V
DDQL
I/O
5L
H13
H14
NC
H15
NC
H16
NC
J1
I/O
12R
J2
NC
J3
V
DDQR
V
SS
J4
J5
V
SS
J6
V
SS
J7
V
SS
J8
V
SS
J9
V
SS
J10
V
SS
J11
V
SS
J12
V
DDQL
J13
NC
J14
NC
J15
I/O
5R
J16
I/O
13L
I/O
14R
I/O
13R
V
DDQL
K1
K2
K3
K4
V
SS
K5
V
SS
K6
V
SS
K7
V
SS
K8
V
SS
K9
V
SS
K10
V
SS
K11
V
SS
V
DDQR
I/O
4R
I/O
3R
I/O
4L
K12
K13
K14
K15
K16
NC
L1
NC
L2
I/O
14L
V
DDQL
V
SS
L3
L4
L5
V
SS
L6
V
SS
L7
V
SS
L8
V
SS
L9
V
SS
L10
V
SS
L11
V
SS
L12
V
DDQR
NC
L13
L14
NC
L15
I/O
3L
L16
I/O
15L
M1
NC
M2
I/O
15R
V
DDQR
V
DD
M3
M4
M5
V
SS
M6
V
SS
M7
V
SS
M8
V
SS
M9
V
SS
M10
V
SS
M11
V
DD
M12
V
DDQL
I/O
2L
M13
M14
NC
M15
I/O
2R
M16
I/O
16R
I/O
16L
N1
N2
NC
N3
V
DDQR
N4
V
DD
N5
V
DD
N6
V
SS
N7
V
SS
N8
V
SS
N9
V
SS
N10
V
DD
N11
V
DD
N12
V
DDQL
I/O
1R
N13
N14
I/O
1L
N15
NC
N16
NC
P1
I/O
17R
P2
NC
P3
PIPE/FT
R
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
P4
P5
P6
P7
P8
P9
P10
P11
P12
V
DD
P13
NC
P14
I/O
0R
P15
NC
P16
NC
R1
I/O
17L
TMS
R2
R3
A
16R
R4
A
13R
R5
A
10R
R6
A
7R
R7
NC
R8
LB
R
R9
CLK
R
ADS
R
R10
R11
A
6R
R12
A
3R
R13
NC
R14
NC
R15
I/O
0L
R16
NC
T1
NC
T2
TRST
T3
NC
T4
A
15R
T5
A
12R
T6
A
9R
T7
UB
R
T8
CE
0R
R/W
R
REPEAT
R
A
4R
T9
T10
T11
T12
A
1R
T13
OPT
R
T14
NC
T15
NC
T16
,
NC
TCK
NC
A
17R
(1)
A
14R
A
11R
A
8R
NC
CE
1R
OE
R
CNTEN
R
A
5R
A
2R
A
0R
NC
NC
5623 drw 02d
NOTES:
1. A
17
is a NC for IDT70V3399.
2. All V
DD
pins must be connected to 3.3V power supply.
3. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is
set to V
IL
(0V).
4. All V
SS
pins must be connected to ground supply.
5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
,
6.42
3
70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration
(1,2,3,4,5,8,9)
(con't.)
A
13L
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
UB
L
LB
L
CE
1L
CE
0L
V
DD
V
DD
V
SS
V
SS
CLK
L
OE
L
R/W
L
ADS
L
CNTEN
L
REPEAT
L
A
6L
A
5L
A
4L
A
3L
A
2L
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
A
14L
A
15L
A
16L
A
17L(1)
IO
9L
IO
9R
V
DDQL
V
SS
IO
10L
IO
10R
V
DDQR
V
SS
IO
11L
IO
11R
IO
12L
IO
12R
V
DD
V
DD
V
SS
V
SS
IO
13R
IO
13L
IO
14R
IO
14L
IO
15R
IO
15L
V
DDQL
V
SS
IO
16R
IO
16L
V
DDQR
V
SS
IO
17R
IO
17L
A
17R(1)
A
16R
A
15R
A
14R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
70V3319/99
PKG128
(6)
128-Pin TQFP
Top View
(7)
A
13R
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
UB
R
LB
R
CE
1R
CE
0R
V
DD
V
DD
V
SS
V
SS
CLK
R
OE
R
R/W
R
ADS
R
CNTEN
R
REPEAT
R
A
6R
A
5R
A
4R
A
3R
A
2R
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
A
1L
A
0L
OPT
L
V
SS
IO
8L
IO
8R
V
SS
V
SS
V
DDQL
IO
7L
IO
7R
V
SS
V
DDQR
IO
6L
IO
6R
IO
5L
IO
5R
V
DD
V
DD
V
SS
V
SS
IO
4R
IO
4L
IO
3R
IO
3L
IO
2R
IO
2L
V
SS
V
DDQL
IO
1R
IO
1L
V
SS
V
DDQR
IO
0R
IO
0L
OPT
R
A
0R
A
1R
5623 drw 02a
NOTES:
1. A
17
is a NC for IDT70V3399.
2. All V
DD
pins must be connected to 3.3V power supply.
3. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is set to V
IL
(0V).
4. All V
SS
pins must be connected to ground supply.
5. Package body is approximately 14mm x 20mm x 1.4mm.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
8. PIPE/FT option in PKG128 is not supported due to limitation in pin count. Device is pipelined outputs only on each port.
9. Due to the limited pin count, JTAG is not supported in the PKG128 package.
6.42
4
70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L
,
CE
1L
R/W
L
OE
L
A
0L
- A
17L
(1)
I/O
0L
- I/O
17L
CLK
L
PIPE/FT
L
(5)
ADS
L
CNTEN
L
REPEAT
L
UB
L
LB
L
V
DDQL
OPT
L
V
DD
V
SS
TDI
TDO
TCK
TMS
TRST
Right Port
CE
0R
,
CE
1R
R/W
R
OE
R
A
0R
- A
17R
(1)
I/O
0R
- I/O
17R
CLK
R
PIPE/FT
R
(5)
ADS
R
CNTEN
R
REPEAT
R
UB
R
LB
R
V
DDQR
OPT
R
Names
Chip Enables
(6)
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Pipeline/Flow-Through
Address Strobe Enable
Counter Enable
Counter Repeat
(4)
Upper Byte Enable (I/O
9
-I/O
17
)
(6)
Lower Byte Enable (I/O
0
-I/O
8
)
(6)
Power (I/O Bus) (3.3V or 2.5V)
(2)
Option for selecting V
DDQX
Power (3.3V)
(2)
Ground (0V)
Test Data Input
Test Data Output
Test Logic Clock (10MHz)
Test Mode Select
Reset (Initialize TAP Controller)
5623 tbl 01
(2,3)
NOTES:
1. A
17
is a NC for IDT70V3399.
2. V
DD
, OPT
X
, and V
DDQX
must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
3. OPT
X
selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X
is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX
must be supplied at 3.3V. If OPT
X
is set to VIL (0V), then that
port's I/Os and address controls will operate at 2.5V levels and V
DDQX
must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
4. When
REPEAT
X
is asserted, the counter will reset to the last valid address loaded
via
ADS
X
.
5. PIPE/FT option in PK-128 package is not supported due to limitation in pin count.
Device is pipelined output mode only on each port.
6. Chip Enables and Byte Enables are double buffered when PL/FT = V
IH
, i.e., the
signals take two cycles to deselect.
6.42
5
实时操作系统RTOS
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