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74HC137
3-to-8 line decoder, demultiplexer with address latches;
inverting
Rev. 4 — 23 December 2015
Product data sheet
1. General description
The 74HC137 is a high-speed Si-gate CMOS device and is pin compatible with low power
Schottky TTL (LSTTL). The 74HC137 is specified in compliance with JEDEC
standard no. 7A.
The 74HC137 is a 3-to-8 line decoder, demultiplexer with latches at the three address
inputs (An). The 74HC137 essentially combines the 3-to-8 decoder function with a 3-bit
storage latch. When the latch is enabled (LE = LOW), the 74HC137 acts as a 3-to-8 active
LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present
at the inputs before this transition, is stored in the latches. Further address changes are
ignored as long as LE remains HIGH.
The output enable input (E1 and E2) controls the state of the outputs independent of the
address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH.
The 74HC137 is ideally suited for implementing non-overlapping decoders in 3-state
systems and strobed (stored address) applications in bus oriented systems.
2. Features and benefits
Combines 3-to-8 decoder with 3-bit latch
Multiple input enable for easy expansion or independent controls
Active LOW mutually exclusive outputs
Low-power dissipation
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from
40 C
to +80
C
and from
40 C
to +125
C.
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC137D
74HC137DB
40 C
to +125
C
40 C
to +125
C
Name
SO16
SSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
Version
SOT109-1
SOT338-1
Type number
NXP Semiconductors
74HC137
3-to-8 line decoder, demultiplexer with address latches; inverting
4. Functional diagram
Fig 1.
Functional diagram
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74HC137
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 23 December 2015
2 of 19
NXP Semiconductors
74HC137
3-to-8 line decoder, demultiplexer with address latches; inverting
Fig 4.
Logic diagram
5. Pinning information
5.1 Pinning
Fig 5.
Pin configuration
74HC137
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 23 December 2015
3 of 19
NXP Semiconductors
74HC137
3-to-8 line decoder, demultiplexer with address latches; inverting
5.2 Pin description
Table 2.
Symbol
A0
A1
A2
LE
E1
E2
Y7
GND
Y6
Y5
Y4
Y3
Y2
Y1
Y0
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
data input 0
data input 1
data input 2
latch enable input (active LOW)
data enable input 1 (active LOW)
data enable input 2 (active HIGH)
multiplexer output 7
ground (0 V)
multiplexer output 6
multiplexer output 5
multiplexer output 4
multiplexer output 3
multiplexer output 2
multiplexer output 1
multiplexer output 0
positive supply voltage
6. Functional description
6.1 Function table
Table 3.
Enable
LE
H
X
X
L
E1
L
H
X
L
E2
H
X
L
H
Function table
[1]
Input
A0
X
X
X
L
H
L
H
L
H
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
Output
A1
X
X
X
L
L
H
H
L
L
H
H
A2
X
X
X
L
L
L
L
H
H
H
H
Y0
stable
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
Y1
Y2
Y3
Y4
Y5
Y6
Y7
74HC137
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 23 December 2015
4 of 19
MEMS传感器
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