MD1711
High Speed, Integrated Ultrasound Driver IC
Features
Drives two ultrasound transducer channels
Generates 5-level waveform
Drives 12 high voltage MOSFETs
±2.0A source and sink peak current
Up to 20MHz output frequency
12V/ns slew rate
±3ns matched delay times
Second harmonic is less than -40dB
Two separate gate drive voltages
1.8V to 3.3V CMOS logic interface
General Description
The Supertex MD1711 is an IC for a two-channel, 5-
level, high voltage and high-speed transmitter driver. It
is designed for medical ultrasound imaging
applications but can also be used for metal flaw
detection, nondestructive evaluation, and driving
piezoelectric transducers.
The MD1711 is a two-channel logic controller circuit
with low impedance MOSFET gate drivers. There are
two sets of control logic inputs, one for channel A and
one for Channel B. Each channel consists of three
pairs of MOSFET gate drivers. These drivers are
designed to match the drive requirements of the
Supertex TC6320. The MD1711 drives six TC6320s.
Each pair an N-channel and a P-channel MOSFET.
They are designed to have the same impedance and
can provide peak currents of over 2.0 amps
.
Applications
Medical ultrasound imaging
Piezoelectric transducer drivers
Metal flaw detection
Nondestructive evaluation
Sonar Transmitter
Typical Application Circuit (1 of 2 Channels)
+5 V
0.22
µF
+1 0 V
-1 0 V
0.22
µF
+1 0 V
0.22
µF
0.22µF
0.22
µF
+10V
FB
6
0.1µF
TC6320
+100V
V
PP
1
1µF
40 36 35
DV
DD
2
AV
DD
1
33 45
43
DGND
42
31
DGND
DV
SS
DV
DD
1
DV
DD
1
30
DGND
DV DD 2
OUTPA1
EN
SEL
POSA / POS1A
NEGA / NEG1A
HVEN1A / POS2A
HVEN2A / NEG2A
ClampA
+3 . 3 V
0.1
µF
47
13
1
2
39
Control Logic
& Level
Translator
10nF
DV DD 2
OUTNA1
37
10nF
V
NN
1
-100V
1µF
3
4
DV DD1
+50V
V
PP
2
1µF
5
46
OUTPA2
MD1711
VL L
41
DV DD1
10nF
(1/2 of I/O)
OUTNA2
34
48
0.1
µF
10nF
V
NN
2
-50V
0V
1µF
AV S S
Transducer
0.1
µF
14
15
AV S S
SU B
OUTPA3
AV
SS
SS
DV DD 1
V
44
OU
TNA3
32
-10V
AGND
DGND
DV
DD
1
D
VSS
DV
DD
2
DV
DD
1
DGND
DV
DD
2
0V
7
0
18
19
16
21
28
26 25
0.22µF
+10V
-10V
+10V
+5V
0
1
Rev.12
011005
MD1711
Ordering Information
Package Option
48-Lead LQFP/TQFP (1.4mm)
MD1711FG
MD1711FG-G
* 10z. 4-layer 3x4inch PCB
-G indicates package is RoHS “Green” compliant
Thermal
Resistance
θ
JA
50°C/W*
Absolute Maximum Ratings*
V
LL
, Logic Supply
AV
DD
1, DV
DD
1, Positive Gate Drive Supply
DV
DD
2, Positive Gate Drive Supply
AV
SS
, DV
SS
Negative Gate Drive Supply
Storage temperature
Junction temperature
Power Dissipation
-0.5V to +5.5V
-0.5V to +15V
-0.5V to +15V
-15V to +0.5V
-65°C to 150°C
125°C
1.2W
*Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional
operation under these conditions is not implied. Continuous operation of the device at the absolute rating level
may affect device reliability. All voltages are referenced to device ground.
Operating Supply Voltages and Currents
(Over operating conditions unless otherwise specified, AV
DD
1 = DV
DD
1 = DV
DD
2 = 10V, AV
SS
= DV
SS
= -10V, V
LL
= 3.3V, T
A
= 25°C)
Sym
V
LL
AV
DD
1
DV
DD
1
DV
DD
2
AV
SS
,
DV
SS
I
VLL
I
AVDD1
I
AVSS
&
I
DVSS
I
DVDD1
I
DVDD2
I
AVDD1Q
I
AVSSQ
I
DVDD1Q
I
DVDD2Q
I
VLLQ
Parameter
Logic Supply
Positive Drive Bias Supply
Positive Gate Drive Supply
Positive Gate Drive Supply
Negative Gate Drive and
Bias Supply
Logic Supply Current
Positive Bias Current
Negative Drive and Bias
Supply Current
Positive Drive Current 1
Positive Drive Current 2
V
AVDD1
quiescent current
V
AVSS
quiescent current
V
DVDD1
quiescent current
V
DVDD2
quiescent current
Logic Supply Current
Min
+1.8
+8.0
+4.75
+4.75
-12.0
Typ
+3.3
+10
Max
+5.5
+12.6
+12.6
+12.6
Units
V
V
V
V
V
mA
mA
Note
-10
2.0
5.0
20
55
13
2.0
0.75
-8.0
All channel on at 5.0Mhz, No load
mA
mA
mA
mA
mA
10
10
1.0
µA
µA
mA
EN = low, All inputs low or high.
DV
DD
2 = 5.0V, All channel on at
5.0Mhz, No load
2
MD1711
DC Electrical Characteristics
(Over operating conditions unless otherwise specified, AV
DD
1 = DV
DD
1 = DV
DD
2 = 10V, AV
SS
= DV
SS
= -10V, V
LL
= 3.3V, T
A
= 0 to 70°C)
P-Channel Gate Driver Outputs
Sym
R
SINK
R
SOURCE
I
SINK
I
SOURCE
Parameter
Output sink resistance
Output source resistance
Peak output sink current
Peak output source current
Min
Typ
Max
6.0
6.0
Units
Ω
Ω
A
A
Conditions
I
SINK
= 100mA
I
SOURCE
= 100mA
2.0
2.0
N-Channel Gate Driver Outputs
Sym
R
SINK
R
SOURCE
I
SINK
I
SOURCE
Parameter
Output sink resistance
Output source resistance
Peak output sink current
Peak output source current
Min
Typ
Max
10
10
Units
Ω
Ω
A
A
Conditions
I
SINK
= 100mA
I
SOURCE
= 100mA
1.5
1.5
Logic Inputs
Sym
V
IH
V
IL
I
IH
I
IL
Parameter
Input logic high voltage
Input logic low voltage
Input logic high current
Input logic low current
Min
0.8V
LL
0
-1.0
Typ
Max
V
LL
0.2V
LL
1.0
Units
V
V
µA
µA
Conditions
AC Electrical Characteristics
(Over operating conditions unless otherwise specified, AV
DD
1 = DV
DD
1 = DV
DD
2 = 10V, AV
SS
= DV
SS
= -10V, V
LL
= 3.3V, T
A
= 0 to 70°C)
Sym
f
OUT
t
PH
t
PL
tr
tf
∆t
dm
∆t
DLAY
SR
HD2
Parameter
Output frequency range
Propagation delay when output
is from low to high
Propagation delay when output
is from high to low
Output rise time
Output fall time
Delay time matching
Output jitter
Output slew rate
2 harmonic distortion
nd
Min
Typ
Max
20
Units
MHz
ns
ns
ns
ns
Conditions
19
19
8.0
8.0
±3.0
30
12
-40
No load, See timing diagram
No load, See timing diagram
1000pF load, see timing diagram
1000pF load, see timing diagram
No load, From device to device
Standard deviation of t
d
samples (1k)
Measured at TC6320 output with
100Ω Load
ns
ps
V/ns
dB
Power-Up Sequence
1
2
AV
SS
, DV
SS
V
LL
, AV
DD
1, DV
DD
1 & DV
DD
2
Negative Gate Drive Supply and Substrate Bias
Logic Supply, Positive Gate Drive Supply and Bias
3
MD1711
Truth Table for Channels A and B (For SEL = L)
Logic Control Inputs
SEL EN HVEN1/
POS2
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
0
X
HVEN2/
NEG2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
Clamp
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
POS/
POS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
NEG/
NEG1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
V
PP
1 to V
NN
1 Output V
PP
2 to V
NN
2 Output
HV
OUT
P1
HV
OUT
N1 HV
OUT
P2
HV
OUT
N2
V
PP
3 to V
NN
3 Output
HV
OUT
P3 HV
OUT
N3
ON
ON
ON
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
4
MD1711
Truth Table for Channels A and B (For SEL = H)
Logic Control Inputs
SEL
EN Clamp
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
HVEN1/
POS2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
HVEN2/
NEG2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
POS/
POS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
NEG/
NEG1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
V
PP
1 to V
NN
1 Output
HV
OUT
P1 HV
OUT
N1
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
V
PP
2 to V
NN
2 Output
HV
OUT
P2 HV
OUT
N2
V
PP
3 to V
NN
3 Output
HV
OUT
P3 HV
OUT
N3
OFF
OFF
OFF
OFF
ON
OFF
ON
OFF
OFF
ON
ON
OFF
OFF
OFF
ON
OFF
ON
ON
ON
OFF
ON
ON
OFF
ON
OFF
ON
OFF
Test Circuit for Channel A
1/2 of MD1711
DV
DD
2
3x TC6320
V
PP
1
Out-PA 1
10nF
GP A1
HV
OUT
PA1
DV
DD
2
+100 V
+10V
AV
DD
1
Out-NA1
10nF
GNA 1
HVout A
+10V DV
DD
1
+10V DV
DD
2
+3.3V V
LL
EN
PO SA / POS1A
NEGA / NEG1A
HVEN1A / POS2A
HVEN2 A / NEG2A
Clam pA
SEL
Channel A
Control
Logic and
Level
Translation
HV
OUT
NA1
V
NN
1
-100V
R
LOAD
100
V
PP
2
DV
DD
1
+50 V
Out-PA 2
10nF
GP A2
HV
OUT
PA2
DV
DD
1
Out-NA2
10nF
GNA 2
HV
OUT
NA2
V
NN
2
-50V
AG nd
DG nd
Out-PA 3
-10V AV
SS
DV
SS
DV
SS
DV
DD
1
GP A3
HV
OUT
PA3
GNA 3
Out-NA3
HV
OUT
NA3
Note: Only one of the two
circuit channels is shown.
5
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