Preliminary
FM24C512
512Kb FRAM Serial Memory
Features
512Kbit Ferroelectric Nonvolatile RAM
Organized as 65,536 x 8 bits
High Endurance 10 Billion (10
10
) Read/Writes
45 year Data Retention
NoDelay Writes
Advanced High-Reliability Ferroelectric Process
Fast Two-wire Serial Interface
Up to 1 MHz Maximum Bus Frequency
Supports Legacy Timing for 100 kHz & 400 kHz
Low Power Operation
5V Operation
250 A Active Current (100 kHz)
120 A Standby Current
Industry Standard Configuration
Industrial Temperature -40 C to +85 C
8-pin Green /RoHS EIAJ SOIC Package
Description
The FM24C512 is a 512-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 45 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
The FM24C512 performs write operations at bus
speed. No write delays are incurred. The next bus
cycle may commence immediately without the need
for data polling. In addition, the product offers write
endurance orders of magnitude higher than
EEPROM. Also, FRAM exhibits much lower power
during writes than EEPROM since write operations
do not require an internally elevated power supply
voltage for write circuits.
These capabilities make the FM24C512 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss. The
combination of features allows more frequent data
writing with less overhead for the system.
The FM24C512 is available in an 8-pin EIAJ SOIC
package using an industry standard two-wire
protocol. Ramtron s green packages are RoHS
compliant. Specifications are guaranteed over an
industrial temperature range of -40°C to +85°C.
Pin Configuration
NC
A1
A2
VSS
1
2
3
4
8
7
6
5
VDD
WP
SCL
SDA
Pin Names
A1,A2
SDA
SCL
WP
VSS
VDD
Function
Device Select Address
Serial Data/Address
Serial Clock
Write Protect
Ground
Supply Voltage 5V
Ordering Information
FM24C512-G
Green /RoHS 8-pin EIAJ SOIC
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Page 1of 12
Rev. 1.0
Aug. 2006
FM24C512
Counter
Address
Latch
8,192 x 64
FRAM Array
8
SDA
Serial to Parallel
Converter
Data Latch
SCL
WP
A1,A2
Control Logic
Figure 1. Block Diagram
Pin Description
Pin Name
A1, A2
Type
Input
Pin Description
Address 1, 2: These pins are used to select one of up to 4 devices of the same type on
the same two-wire bus. To select the device, the address value on the two pins must
match the corresponding bits contained in the device address. The address pins are
pulled down internally.
Write Protect: When WP is high, the entire array will be write-protected. When WP is
low, all addresses may be written. This pin is internally pulled down.
Serial Data/Address: This is a bi-directional input used to shift serial data and
addresses for the two-wire interface. It employs an open-drain output and is intended
to be wire-OR d with other devices on the two-wire bus. The input buffer incorporates
a Schmitt trigger for improved noise immunity and the output driver has slope control
for falling edges. An external pull-up resistor is required.
Serial Clock: The serial clock input for the two-wire interface. Data is clocked out of
the device on the SCL falling edge, and clocked in on the SCL rising edge. The SCL
input also incorporates a Schmitt trigger input for improved noise immunity.
Supply Voltage: 5V
Ground
WP
SDA
Input
I/O
SCL
Input
VDD
VSS
Supply
Supply
Rev. 1.0
Aug. 2006
Page 2 of 12
FM24C512
Overview
The FM24C512 is a serial FRAM memory. The
device has 65,536 locations with 8 data bits each and
is accessed using an industry standard two-wire
interface. Functional operation of the FRAM is
similar to serial EEPROMs. The major difference
between the FM24C512 and a serial EEPROM
relates to its superior write performance.
Two-wire Interface
The FM24C512 employs a bi-directional two-wire
bus protocol using few pins and little board space.
Figure 2 illustrates a typical system configuration
using the FM24C512 in a microcontroller-based
system. The industry standard two-wire bus is
familiar to many users but is described in this section.
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM24C512 is always a slave device.
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions
including Start, Stop, Data bit, and Acknowledge.
Figure 3 illustrates the signal conditions that specify
the four states. Detailed timing diagrams are shown
in the Electrical Specifications section.
V
DD
Memory Architecture
The FM24C512 is logically organized as two 32,768
x 8 bit memory arrays for a total of 65,536 locations.
The device should be treated as two banks, each bank
being selectable by the most significant address bit
A15. The MSB is located in the Slave Address byte
and can be considered a bank select bit. See Figure 4.
Data bits are shifted serially into and out of the
device. The 65,536 addresses are accessed using the
two-wire protocol, which includes a Slave Address
(to distinguish from other non-memory devices), and
a 16-bit address.
The memory is read or written at the speed of the
two-wire bus. Unlike an EEPROM, it is not
necessary to poll the device for a ready condition
since writes occur at bus speed. By the time a new
bus transaction can be shifted into the part, a write
operation is complete. This is explained in more
detail in the interface section below.
Users can expect several obvious system benefits
from the FM24C512 due to its fast write cycle and
high endurance as compared with EEPROM.
However there are less obvious benefits as well. For
example in a high noise environment, the fast-write
operation is less susceptible to corruption than an
EEPROM since the write cycle is completed quickly.
By contrast, an EEPROM requiring milliseconds to
write is vulnerable to noise during much of the cycle.
Note that the FM24C512 contains no power
management circuits other than a simple internal
power-on reset. It is the user s responsibility to
ensure that V
DD
is maintained within data sheet
tolerances to prevent incorrect operation.
R
min
= 1.8 K?
R
max
= t
R
/C
bus
Microcontroller
SDA
SCL
SDA
SCL
FM24C512
A1 A2
V
DD
FM24C512
A1 A2
Figure 2. Typical System Configuration
Rev. 1.0
Aug. 2006
Page 3 of 12
FM24C512
7
Stop
(Master)
Start
(Master)
6
0
Data bit Acknowledge
(Transmitter) (Receiver)
Data bits
(Transmitter)
Figure 3. Data Transfer Protocol
Stop Condition
A Stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations using the FM24C512 must end
with a Stop condition. If an operation is pending
when a Stop is asserted, the operation will be aborted.
The master must have control of SDA (not a memory
read) in order to assert a Stop condition.
Start Condition
A Start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All read and write transactions begin with a
Start condition. An operation in progress can be
aborted by asserting a Start condition at any time.
Aborting an operation using the Start condition will
ready the FM24C512 for a new operation.
If during operation the power supply drops below the
specified V
DD
minimum, the system should issue a
Start condition prior to performing another operation.
Data/Address Transfer
All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high.
Acknowledge
The Acknowledge takes place after the 8
th
data bit
has been transferred in any transaction. During this
state the transmitter should release the SDA bus to
allow the receiver to drive it. The receiver drives the
SDA signal low to acknowledge receipt of the byte.
If the receiver does not drive SDA low, the condition
is a No-Acknowledge and the operation is aborted.
The receiver would fail to acknowledge for two
distinct reasons. First is that a byte transfer fails. In
this case, the No-Acknowledge terminates the current
operation so that the part can be addressed again.
This allows the last byte to be recovered in the event
of a communication error.
Second and most common, the receiver does not
acknowledge to deliberately end an operation. For
example, during a read operation, the FM24C512
will continue to place data onto the bus as long as
the receiver sends Acknowledges (and clocks).
When a read operation is complete and no more data
is needed, the receiver must not acknowledge the
last byte. If the receiver acknowledges the last byte,
this will cause the FM24C512 to attempt to drive the
bus on the next clock while the master is sending a
new command such as Stop.
Slave Address
The first byte that the FM24C512 expects after a
Start condition is the Slave Address. As shown in
Figure 4, the Slave Address contains the Slave ID
(device type), the device select bits (A1, A2), the
MSB (A15) of the two-byte address, and a bit that
specifies if the transaction is a read or a write. Bits
7-4 define the device type and must be set to 1010b
for the FM24C512. These bits allow other types of
function types to reside on the 2-wire bus within an
identical address range. Bits 3-2 are the device
select bits which are equivalent to chip select bits.
They must match the corresponding value on the
external address pins to select the device. Up to four
FM24C512 devices can reside on the same two-wire
bus by assigning a different address to each. Bit 1 is
the most significant address bit and acts like a bank
select bit. This is important to understand when the
device automatically increments the address at the
7FFFh and FFFFh boundaries (covered in the next
section). Bit 0 is the read/write bit. A 1 indicates a
read operation, and a 0 indicates a write.
Slave ID
Device
Select
Address
MSB
1
7
0
6
1
5
0
4
A2
3
A1
2
A15
1
R/W
0
Figure 4. Slave Address
Rev. 1.0
Aug. 2006
Page 4 of 12
FM24C512
Addressing Overview
After the FM24C512 (as receiver) acknowledges the
Slave Address, the master can drive the remaining
portion of the memory address for a write operation.
The complete address is specified by the A15 bit in
the Slave Address and two additional bytes (A14-
A0). The first address byte specifies A14 A8, where
the first of the eight bits is a don t care . Following
the upper address byte is the lower byte (A7 A0).
The address value A(14:0) is latched internally. The
MSB A15 is not latched. Each access causes the
latched address value to be incremented
automatically. The current address is the value that is
held in the latch, either a newly written value or the
address following the last access. The current address
will be held as long as power remains or until a new
value is written. Reads always use the current
address, however A15 must be specified. A random
read address can be loaded by starting a write
operation as explained below.
After transmission of each data byte, just prior to the
acknowledge, the FM24C512 increments the internal
address latch. This allows the next sequential byte to
be accessed with no additional addressing externally.
When auto-incrementing, the user must be aware that
the address DOES NOT increment from 7FFFh to
8000h and DOES NOT wrap from FFFFh to 0000h.
The memory should be treated as two separate
address spaces, an upper and lower. When the last
address in the lower half (7FFFh) is reached, the
address rolls over to 0000h. Likewise when the last
address in the upper half (FFFFh) is reached, the
address rolls over to 8000h.
Data Transfer
After the address information has been transmitted,
data transfer between the bus master and the
FM24C512 can begin. For a read operation the
FM24C512 will place 8 data bits on the bus then wait
for an Acknowledge from the master. If the
Acknowledge occurs, the FM24C512 will transfer the
next sequential byte. If the Acknowledge is not sent,
the FM24C512 will end the read operation. For a
write operation, the FM24C512 will accept 8 data
bits from the master then send an acknowledge. All
data transfer occurs MSB (most significant bit) first.
operation for both writes and reads is explained
below.
Write Operation
All writes begin with a Slave Address, then a
memory address. The bus master indicates a write
operation by setting the LSB of the Slave Address to
a 0 . After addressing, the bus master sends each
byte of data to the memory and the memory
generates an Acknowledge condition. Sequential
bytes may be written through the address space
however care must be taken when auto-
incrementing. The memory is separated into an
upper and lower address space. The auto-increment
feature of the device will cause the address to wrap
from 7FFFh to 0000h in the lower half and wrap
from FFFFh to 8000h for the upper half of the
memory.
Unlike other nonvolatile memory technologies,
there is essentially no write delay with FRAM.
Since the read and write access times of the
underlying memory are the same, the user
experiences no delay on the bus. The entire memory
cycle occurs in less time than a single bus clock.
Therefore, any operation including a read or write
can occur immediately following a write.
Acknowledge polling, a technique used with
EEPROMs to determine if a write has completed is
unnecessary and will always return a ready
condition.
Internally, an actual memory write occurs after the
8
th
data bit is transferred. It will be complete before
the Acknowledge is sent. Therefore, if the user
desires to abort a write without altering the memory
contents, this should be done using a Start or Stop
condition prior to the 8
th
data bit. The FM24C512
uses no page buffering.
The memory array can be write protected using the
WP pin. Pulling the WP pin high will write-protect
all addresses. The FM24C512 will not acknowledge
data bytes that are written when WP is active. In
addition, the address counter will not increment if
writes are attempted to these addresses. Setting WP
low will deactivate this feature. WP is internally
pulled down. The state of WP should remain stable
from the Start command until the address is
complete.
Figure 5 and 6 below illustrate both a single-byte
and multiple-write.
Memory Operation
The FM24C512 is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of FRAM
technology. These improvements result in some
differences between the FM24C512 and a similar
configuration EEPROM during writes. The complete
Rev. 1.0
Aug. 2006
Page 5 of 12
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