FemtoClock
®
NG Crystal-to-HCSL
Clock Generator
G
ENERAL
D
ESCRIPTION
The 841654 is an optimized PCIe and sRIO clock generator.
The device uses a 25MHz parallel crystal to generate 100MHz
and 125MHz clock signals, replacing solutions requiring multiple
oscillator and fanout buffer solutions. The device has excellent phase
jitter (< 1ps rms) suitable to clock components requiring precise and
low-jitter PCIe or sRIO or both clock signals. Designed for telecom,
networking and industrial applications, the 841654 can also drive the
high-speed sRIO and PCIe SerDes clock inputs of communication
processors, DSPs, switches and bridges.
841654
DATASHEET
F
EATURES
• Four differential HCSL clock outputs: configurable for PCIe
(100MHz) and sRIO (100MHz or 125MHz) clock signals
One REF_OUT LVCMOS/LVTTL clock output
• Selectable crystal oscillator interface, 25MHz, 18pF parallel reso-
nant crystal or LVCMOS/LVTTL single-ended reference
clock input
• Supports the following output frequencies:
100MHz or 125MHz
• VCO: 500MHz
• PLL bypass and output enable
• RMS phase jitter at 100MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.44ps (typical)
• Full 3.3V power supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
B
LOCK
D
IAGRAM
XTAL_IN
P
IN
A
SSIGNMENT
1
QA0
nQA0
OSC
XTAL_OUT
REF_IN
Pulldown
REF_SEL
Pulldown
0
FemtoClock
PLL
1
VCO = 500MHz
0
÷NA
QA1
nQA1
V
DD
REF_OUT
GND
QA0
nQA0
V
DDOA
GND
QA1
nQA1
nREF_OE
BYPASS
REF_IN
REF_SEL
V
DDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
M = ÷20
IREF
QB0
nQB0
÷NB
BYPASS
Pulldown
QB1
nQB1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
IREF
FSEL0
FSEL1
QB0
nQB0
V
DDOB
GND
QB1
nQB1
MR/nOE
V
DD
XTAL_IN
XTAL_OUT
GND
FSEL[0:1]
Pulldown
MR/nOE
Pulldown
841654
28-Lead TSSOP
6.1mm x 9.7mm x 0.925mm
package body
G Package
Top View
REF_OUT
Pullup
nREF_OE
841654 REVISION A 4/20/15
1
©2015 Integrated Device Technology, Inc.
841654 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 18
2
3, 7, 15, 22
4, 5,
8, 9
6
10
11
12
13
14
16, 17
Name
V
DD
REF_OUT
GND
QA0, nQA0,
QA1, nQA1
V
DDOA
nREF_OE
BYPASS
REF_IN
REF_SEL
V
DDA
XTAL_OUT,
XTAL_IN
Power
Output
Power
Ouput
Power
Input
Input
Input
Input
Power
Input
Pullup
Type
Description
Core supply pins.
Single-ended reference frequency clock output.
LVCMOS/LVTTL interface levels.
Power supply ground.
Differential Bank A output pairs. HCSL interface levels.
Output supply pin for Bank A outputs.
Active low REF_OUT enable/disable. See Table 3E.
LVCMOS/LVTTL interface levels.
Selects PLL operation/PLL bypass operation.
Pulldown
See Table 3C. LVCMOS/LVTTL interface levels.
Single-ended PLL reference clock input.
Pulldown
LVCMOS/LVTTL interface levels.
Reference select. Selects the input reference source.
Pulldown
See Table 3B. LVCMOS/LVTTL interface levels.
Analog supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input. (PLL reference.)
Active HIGH master reset. Active LOW output enable. When logic HIGH, the
internal dividers are reset and the differential outputs are in high impedance
Pulldown
(HiZ). When logic LOW, the internal dividers and the differential outputs are
enabled. See Table 3D. LVCMOS/LVTTL interface levels.
Differential Bank B output pairs. HCSL interface levels.
Output supply pin for Bank B outputs.
Pulldown Output frequency select pins. LVCMOS/LVTTL interface levels.
HCSL current reference external resistor output. A fixed precision resistor
(RREF = 475Ω) from this pin to ground provides a reference current used
for differential current-mode QA[0:1]/nQA[0:1] and QB[0:1]/nQB[0:1] clock
outputs.
19
MR/nOE
Input
20, 21
24, 25
23
26, 27
nQB1, QB1
nQB0, QB0
V
DDOB
FSEL1,
FSEL0
IREF
Output
Power
Input
28
Output
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input PullupResistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
2
REVISION A 4/20/15
841654 DATA SHEET
T
ABLE
3A. FSEL
X
F
UNCTION
T
ABLE
(f
Inputs
FSEL1
0
0
1
1
FSEL0
0
1
0
1
M
20
20
20
20
ref
= 25MH
Z
)
Outputs Frequency Settings
QA0:1/nQA0:1
VCO/5 (100MHz)
VCO/5 (100MHz)
VCO/5 (100MHz)
VCO/4 (125MHz)
QB0:1/nQB0:1
VCO/5 (100MHz) (default)
VCO/4 (125MHz)
QB0:1 = L, nQB0:1 = H
VCO/4 (125MHz)
T
ABLE
3B. REF_SEL F
UNCTION
T
ABLE
Input
REF_SEL
0
1
Input Reference
XTAL (default)
REF_IN
T
ABLE
3C. BYPASS F
UNCTION
T
ABLE
Input
BYPASS
0
1
PLL Configuration
NOTE 1
PLL on (default)
PLL bypassed (QA, QB = fref/N)
NOTE 1: Asynchronous function.
T
ABLE
3D. MR/nOE F
UNCTION
T
ABLE
Input
MR/nOE
0
1
Function
NOTE 1
Outputs enabled (default)
Device reset, outputs disabled (High Impedance)
NOTE 1: Asynchronous function.
T
ABLE
3E. nREF_OE F
UNCTION
T
ABLE
Input
nREF_OE
0
1
Function
NOTE 1
REF_OUT enabled
REF_OUT disabled (High Impedance) (default)
NOTE 1: Asynchronous function.
REVISION A 4/20/15
3
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841654 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDOX
+ 0.5V
64.4°C/W (0 lfpm)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
C
HARACTERISTICS
,
V
DD
= V
DDOA
= V
DDOB
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDOA,
V
DDOB
I
DD
I
DDA
I
DDOA
and
I
DDOB
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Unterminated
Unterminated
Unterminated, RREF = 475 ± 1%
Ω
Test Conditions
Minimum
3.135
V
DD
– 0.20
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
85
20
5
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
REF_IN, REF_SEL,
BYPASS, MR/nOE,
FSEL0, FSEL1
nREF_OE
REF_IN, REF_SEL,
BYPASS, MR/nOE,
FSEL0, FSEL1
nREF_OE
V
OH
V
OL
Z
OUT
Ouput High Voltage;
NOTE 1
Ouput Low Voltage;
NOTE 1
Output Impedance
REF_OUT
REF_OUT
REF_OUT
V
DD
= V
IN
= 3.465 V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V
V
DD
= 3.465V
V
DD
= 3.465V
20
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
Input High Current
I
IL
Input Low Current
-150
2.6
0.5
µA
V
V
Ω
NOTE 1: Outputs terminated with 50Ω to V
DD
/2. See Parameter Measurement Information Section,
Output Load Test Circuit diagram.
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
4
REVISION A 4/20/15
841654 DATA SHEET
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
Test Conditions
Minimum
Typical
25
50
7
Maximum
Units
MHz
Ω
pF
Fundamental
T
ABLE
6A. LVCMOS AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
R
F
Parameter
Output Frequency
Output Duty Cycle
REF_OUT
Output Rise/Fall Time
Test Conditions
20% to 80%
Minimum
0.60
49
Typical
25
Maximum
1.80
51
Units
MHz
ns
%
t /t
odc
T
ABLE
6B. HCSL AC C
HARACTERISTICS
,
V
DD
= V
DDOA
= V
DDOB
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
Parameter
Output Frequency
Test Conditions
VCO/5
VCO/4
100MHz,
(1.875MHz - 20MHz)
125MHz,
(1.875MHz - 20MHz)
Minimum
Typical
100
125
0.44
0.44
Maximum
Units
MHz
MHz
ps
ps
t
jit(Ø)
t
jit(cc)
t
sk(o)
t
L
HIGH
LOW
OVS
UDS
rb
CROSS
RMS Phase Jitter (Random);
NOTE 1
Cycle-to-Cycle Jitter; NOTE 3
Output Skew;
NOTE 2, 3
PLL Lock Time
Voltage High
Voltage Low
Max. Voltage, Overshoot
Min. Voltage, Undershoot
Ringback Voltage
Absolute Crossing Voltage
Total Variation of V
CROSS
35
100
100
125MHz
650
-150
-0.3
0.2
200
550
160
measured between
0.175V to 0.525V
100
700
125
52
700
950
150
0.3
ps
ps
ms
mV
mV
V
V
V
mV
mV
ps
ps
%
QAx/nQAx,
QBx/nQBx
V
V
V
V
V
V
Δ
V
CROSS
t /t
R
F
over all edges
QAx/nQAx,
QBx/nQBx
Output Rise/Fall Time
Rise/Fall Time Variation
Output Duty Cycle
Δ
t
R
/
Δ
t
F
odc
QAx/nQAx,
48
QBx/nQBx
NOTE: All specifications are taken at 100MHz and 125MHz.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
REVISION A 4/20/15
5
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
嵌入式系统
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