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74AUP2G07GF

产品描述Low-power dual buffer with open-drain output
文件大小67KB,共16页
制造商Philips Semiconductors (NXP Semiconductors N.V.)
官网地址https://www.nxp.com/
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74AUP2G07GF概述

Low-power dual buffer with open-drain output

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74AUP2G07
Low-power dual buffer with open-drain output
Rev. 02 — 12 June 2007
Product data sheet
1. General description
The 74AUP2G07 provides two non-inverting buffers with open-drain output. The output of
the device is an open drain and can be connected to other open-drain outputs to
implement active-LOW wired-OR or active-HIGH wired-AND functions.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features
s
Wide supply voltage range from 0.8 V to 3.6 V
s
High noise immunity
s
Complies with JEDEC standards:
x
JESD8-12 (0.8 V to 1.3 V)
x
JESD8-11 (0.9 V to 1.65 V)
x
JESD8-7 (1.2 V to 1.95 V)
x
JESD8-5 (1.8 V to 2.7 V)
x
JESD8-B (2.7 V to 3.6 V)
s
ESD protection:
x
HBM JESD22-A114E Class 3A exceeds 5000 V
x
MM JESD22-A115-A exceeds 200 V
x
CDM JESD22-C101C exceeds 1000 V
s
Low static-power consumption; I
CC
= 0.9
µA
(maximum)
s
Latch-up performance exceeds 100 mA per JESD 78 Class II
s
Inputs accept voltages up to 3.6 V
s
Low noise overshoot and undershoot < 10 % of V
CC
s
I
OFF
circuitry provides partial Power-down mode operation
s
Multiple package options
s
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C

74AUP2G07GF相似产品对比

74AUP2G07GF 74AUP2G07 74AUP2G07GM 74AUP2G07GW
描述 Low-power dual buffer with open-drain output Low-power dual buffer with open-drain output Low-power dual buffer with open-drain output Low-power dual buffer with open-drain output

 
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