DATASHEET
NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER
Description
The ICS680-01 generates four high-frequency clock outputs
and a reference from a 25 MHz crystal or clock input. The
device includes a low-skew, single input to four output zero
delay clock buffer. It can replace multiple crystals and
oscillators, saving board space and cost.
The device has a power-down tri-state (PDTS) pin that place
the clock outputs in a high-impedance state when pulled
low. The PDTS pin includes an internal pull-up resistor.
ICS680-01
Features
•
•
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•
•
•
•
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Packaged in 24-pin TSSOP
Pb (lead) free package, RoHS compliant
Replaces multiple crystals and oscillators
Input crystal or clock frequency of 25 MHz
Five output driver driven by external clock
Duty cycle of 45/55
Operating voltage of 3.3 V
Advanced, low-power CMOS process
Fixed output frequencies of 25 MHz and 48 MHz
Selectable output frequencies of 24 MHz, 48 MHz, 50
MHz and 66.6666 MHz
•
Qx outputs replace costly discrete buffer
•
Low-skew buffer outputs (250 ps)
Block Diagram
VDD
5
S0
S1
PLLA
Divide
Logic
and
Output
Enable
Control
CLK2
48M
25M
CLK1
PLLB
25 MHz
Crystal or Clock
X1/ICLK
Crystal
Oscillator
PLLC
X2
External capacitors
may be required.
QFB
Q0
Q1
PLL/Buffer
Q2
Q3
2
GND
PDTS
ICLK
IDT™ / ICS™
NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER 1
ICS680-01
REV H 051310
ICS680-01
NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER
ZDB AND SYNTHESIZER
Pin Assignment
X1/ICLK
GND
S0
VDD
CLK1
GND
GND
Q1
Q2
VDD
Q3
Q4
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
X2
VDD
PDTS
S1
25M
ICLK
VDD
QFB
VDD
48M
CLK2
GND
Output Clock Select Table
S0
M
0
0
1
1
S1
M
0
1
0
1
CLK1 (MHz) CLK2 (MHz)
OFF
50
66.6666
50
66.6666
48
48
48
24
24
24-pin TSSOP
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Pin
Name
X1/ICLK
GND
S0
VDD
CLK1
GND
GND
Q1
Q2
VDD
Q3
Q4
GND
CLK2
48M
VDD
QFB
Pin
Type
XI
Power
Input
Power
Output
Power
Power
Output
Output
Power
Output
Output
Power
Output
Output
Power
Output
Connect to ground.
Pin Description
Crystal input. Connect this pin to a crystal or external clock source.
Select pin 0. See table above.
Connect to voltage supply.
Selectable output clock. See table above. Weak internal pull-down when
tri-state.
Connect to ground.
Connect to ground.
Clock output 1. Weak internal pull-down when tri-state.
Clock output 2. Weak internal pull-down when tri-state.
Connect to voltage supply.
Clock output 3. Weak internal pull-down when tri-state.
Clock output 4. Weak internal pull-down when tri-state.
Connect to ground.
Selectable output clock. See table above. Weak internal pull-down when
tri-state.
48 MHz output clock. Weak internal pull-down when tri-state.
Connect to voltage supply.
Feedback pin. Internally connected.
IDT™ / ICS™
NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER 2
ICS680-01
REV H 051310
ICS680-01
NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER
ZDB AND SYNTHESIZER
Pin
Number
18
19
20
21
22
23
24
Pin
Name
VDD
ICLK
25M
S1
PDTS
VDD
X2
Pin
Type
Power
Input
Output
Input
Power
Power
XO
Connect to voltage supply.
Pin Description
Zero Delay Buffer Input. Weak Internal pull-up.
25 MHz reference output clock. Weak internal pull-down when tri-state.
Select pin 1. See table above.
Power-down tri-state. Powers down entire chip and tri-states outputs
when low. Internal pull-up resistor.
Connect to voltage supply.
Crystal output. Connect this pin to a crystal. Float for clock input.
External Components
The ICS680-01 requires a minimum number of external
components for proper operation.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) To minimize EMI, the 33Ω series termination resistor (if
needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
ICS680-01. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD (pins 5 and 16) and GND (pins 6 and 15), as
close to these pins as possible. For optimum device
performance, the decoupling capacitor should be mounted
on the component side of the PCB. Avoid the use of vias in
the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
impedance) place a 33Ω resistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω
.
Crystal Information
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant. Crystal capacitors should
be connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these capacitors
is given by the following equation crystal caps (pF) =
(C
L
-6)x2
In the equation, C
L
is the crystal load capacitance. So for a
crystal with a 16 pF load capacitance, two 20 pF[(16-6)x2]
capacitors should be used
IDT™ / ICS™
NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER 3
ICS680-01
REV H 051310
ICS680-01
NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER
ZDB AND SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS680-01. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-65 to +150° C
125° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.13
Typ.
+3.3
Max.
+70
+3.46
Units
°
C
V
IDT™ / ICS™
NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER 4
ICS680-01
REV H 051310
ICS680-01
NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER
ZDB AND SYNTHESIZER
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%,
Ambient Temperature 0 to +70° C
Parameter
Operating Voltage
Supply Current
Input High Voltage, binary
inputs
Input High Voltage, trinary
inputs
Input Low Voltage, binary
inputs
Input Low Voltage, trinary
inputs
Output High Voltage
Output High Voltage
Output Low Voltage
Short Circuit Current
Input Capacitance, Inputs
Nominal Output
Impedance
On-Chip Pull-up Resistor,
Inputs
On-Chip Pull-down
Resistor, Outputs
Symbol
VDD
IDD
V
IH
V
IH
V
IL
V
IL
V
OH
V
OH
V
OL
I
OS
C
IN
Z
OUT
R
PU
R
PD
Conditions
No load,PDTS=1
No load,PDTS=0
PDTS, ICLK
S0, S1
PDTS, ICLK
S0, S1
I
OH
= -4 mA
I
OH
= -12 mA
I
OL
= 12 mA
I
OL
= 4 mA
CLK output
Min.
3.13
Typ.
3.3
32
300
Max.
3.46
Units
V
mA
µA
V
V
2
VDD-0.5
0.8
0.5
VDD-0.4
2.4
0.8
0.4
±50
5
20
V
V
V
V
V
V
mA
pF
Ω
kΩ
kΩ
PDTS, SEL
CLK outputs
250
250
IDT™ / ICS™
NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER 5
ICS680-01
REV H 051310
DSP 与 ARM 处理器
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