Philips Semiconductors
Product specification
4-bit parallel access shift register
FEATURES
•
Asynchronous master reset
•
J, K, (D) inputs to the first stage
•
Fully synchronous serial or parallel data transfer
•
Shift right and parallel load capability
•
Complement output from the last stage
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT195 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT195 performs serial, parallel,
serial-to-parallel or parallel-to-serial data transfer at very
high speeds. The “195” operates on two primary modes:
shift right (Q
o
→Q
1
) and parallel load, which are controlled
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT195
by the state of the parallel load enable (PE) input. Serial
data enters the first flip-flop (Q
0
) via the J and K inputs
when the PE input is HIGH and shifted one bit in the
direction Q
0
→
Q
1
→
Q
2
→
Q
3
following each
LOW-to-HIGH clock transition. The J and K inputs provide
the flexibility of the JK type input for special applications
and by tying the pins together, the simple D-type input for
general applications. The “195” appears as four common
clocked D flip-flops when the PE input is LOW.
After the LOW-to-HIGH clock transition, data on the
parallel inputs (D
0
to D
3
) is transferred to the respective
Q
0
to Q
3
outputs. Shift left operation (Q
3
→
Q
2
) can be
achieved by tying the Q
n
outputs to the D
n-1
inputs and
holding the PE input LOW.
All parallel and serial data transfers are synchronous,
occurring after each LOW-to-HIGH clock transition.
There is no restriction on the activity of the J, K, D
n
and
PE inputs for logic operation other than the set-up and
hold time requirements. A LOW on the asynchronous
master reset (MR) input sets all Q outputs LOW,
independent of any other input condition.
TYPICAL
SYMBOL
t
PHL
/ t
PLH
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
)
where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1,5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PARAMETER
propagation delay CP to Q
n
maximum clock frequency
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
15
57
3.5
105
HCT
15
57
3.5
105
ns
MHz
pF
pF
UNIT
December 1990
2
Philips Semiconductors
Product specification
4-bit parallel access shift register
74HC/HCT195
Fig.4 Functional diagram.
APPLICATIONS
•
Serial data transfer
•
Parallel data transfer
•
Serial-to-parallel data transfer
•
Parallel-to-serial data transfer
FUNCTION TABLE
INPUTS
OPERATING MODES
MR
asynchronous reset
shift, set first stage
shift, reset first stage
shift, toggle first stage
shift, retain first stage
parallel load
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q, d = lower case letters indicate the state of the referenced input (or output) one set-up time prior to the
LOW-to-HIGH clock transition
X = don’t care
↑
= LOW-to-HIGH clock transition
L
H
H
H
H
H
CP
X
↑
↑
↑
↑
↑
PE
X
h
h
h
h
l
J
X
h
l
h
l
X
K
X
h
l
l
h
X
D
n
X
X
X
X
X
d
n
Q
0
L
H
L
q0
q0
d
0
Q
1
L
q0
q0
q0
q0
d
1
Q
2
L
q1
q1
q1
q1
d
2
Q
3
L
q2
q2
q2
q2
d
3
Q
3
H
q2
q2
q2
q2
d
3
OUTPUTS
December 1990
4
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