IDTCSPUA877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
1.8V PHASE LOCKED LOOP
DIFFERENTIAL 1:10 SDRAM
CLOCK DRIVER
FEATURES:
DESCRIPTION:
IDTCSPUA877A
• 1 to 10 differential clock distribution
• Optimized for clock distribution in DDR2 (Double Data Rate)
SDRAM applications
• Operating frequency: 125MHz to 410MHz
• Stabilization time: <6us
• Very low skew:
≤
40ps
• Very low jitter:
≤
40ps
• 1.8V AV
DD
and 1.8V V
DDQ
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 52-Ball VFBGA and 40-pin VFQFPN packages
APPLICATIONS:
• Meets or exceeds JEDEC standard CUA877 for registered DDR2
clock driver
• Along with SSTUA32864/66, DDR2 register, provides complete
solution for DDR2 DIMMs
The CSPUA877A is a PLL based clock driver that acts as a zero delay buffer
to distribute one differential clock input pair(CLK,
CLK
) to 10 differential
output pairs (Y
[0:9]
, Y
[0:9]
) and one differential pair of feedback clock output
(FBOUT,
FBOUT).
External feedback pins (FBIN,
FBIN)
for synchronization
of the outputs to the input reference is provided. OE, OS, and A
VDD
control the
power-down and test mode logic. When A
VDD
is grounded, the PLL is turned
off and bypassed for test mode purposes. When the differential clock inputs
(CLK,
CLK)
are both at logic low, this device will enter a low power-down mode.
In this mode, the receivers are disabled, the PLL is turned off, and the output
clock drivers are disabled, resulting in a clock driver current consumption of less
than 500μA.
The CSPUA877A requires no external components and has been optimised
for very low phase error, skew, and jitter, while maintaining frequency and duty
cycle over the operating voltage and temperature range. The CSPUA877 ,
designed for use in both module assemblies and system motherboard based
solutions, provides an optimum high-performance clock source.
The CSPUA877A is available in Commercial Temperature Range (0°C to
+70°C). See Ordering Information for details.
FUNCTIONAL BLOCK DIAGRAM
OE
OS
AV
DD
LD or OE
POWER
DOWN
AND
LD, OS, or OE
TEST
MODE
PLL BYPASS
LOGIC
LD
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
CLK
CLK
10KΩ - 100KΩ
FBIN
FBIN
PLL
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
NOTE:
The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and
CLK.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Y9
FBOUT
COMMERCIAL TEMPERATURE RANGE
1
c
2006 Integrated Device Technology, Inc.
FBOUT
OCTOBER 2006
DSC 6872/4
IDTCSPUA877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
6
Y
6
Y
5
Y
5
Y
6
GND
GND
Y
7
GND
NB
NB
GND
Y
2
C
Y
7
OS
V
DDQ
FBIN
V
DDQ
NB
NB
FBIN FBOUT FBOUT
OE
NB
NB
GND
NB
NB
GND
Y
8
Y
8
Y
9
Y
9
5
V
DDQ
V
DDQ
GND
GND
4
3
Y
0
Y
0
Y
1
A
GND
GND
Y
1
B
V
DDQ
V
DDQ
V
DDQ
GND
GND
Y
3
J
Y
4
Y
4
Y
3
K
2
V
DDQ
V
DDQ
V
DDQ
Y
2
D
1
CLK
E
CLK
F
AGND AV
DD
G
H
VFBGA
TOP VIEW
52 BALL VFBGA PACKAGE LAYOUT
0.65mm
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
TOP VIEW
A
1
2
3
4
5
6
B
C
D
E
F
G
H
J
K
2
IDTCSPUA877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION, CONT.
V
DDQ
V
DDQ
ABSOLUTE MAXIMUM RATINGS
(1,2)
Symbol
V
DDQ
, AV
DD
V
I(3)
V
O(3)
I
IK
(V
I
<0)
I
OK
(V
O
<0 or
V
O
> V
DDQ
)
I
O
(V
O
=0 to V
DDQ
)
V
DDQ
or GND
TSTG
Rating
Supply Voltage Range
Input Voltage Range
Voltage range applied to any
output in the high or low state
Input clamp current
Output Clamp Current
Max
–0.5 to +2.5
–0.5 to V
DDQ
+ 0.5
–0.5 to V
DDQ
+ 0.5
±50
±50
Unit
V
V
V
mA
mA
Y
1
Y
1
Y
0
Y
0
Y
5
Y
6
39
32
Y
6
Y
5
40
38
37
36
35
33
34
31
V
DDQ
Y
2
Y
2
CLK
CLK
V
DDQ
AGND
AV
DD
V
DDQ
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
30
29
28
27
26
GND
25
24
23
22
21
Y
7
Y
7
V
DDQ
FBIN
FBIN
FBOUT
FBOUT
V
DDQ
OE
OS
Continuous Output Current
Continuous Current
Storage Temperature Range
±50
±100
– 65 to +150
mA
mA
°C
VFQFPN
TOP VIEW
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The maximum package power dissipation is calculated using a junction temperature
of 150
°
C and a board trace length of 750 mils.
3. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed. This value is limited to 2.5V max.
Y
4
V
DDQ
V
DDQ
Y
3
Y
3
Y
4
Y
9
Y
9
Y
8
Y
8
CAPACITANCE
(1)
Parameter
C
IN
C
I
Δ
C
L
Description
Input Capacitance
V
I
= V
DDQ
or GND
Delta Input Capacitance
CLK,
CLK,
FBIN,
FBIN
Load Capacitance
—
10
—
pF
NOTE:
1. Unused inputs must be held high or low to prevent them from floating.
Min.
2
Typ.
—
Max.
3
0.25
Unit
pF
pF
RECOMMENDED OPERATING CONDITIONS
Symbol
AV
DD(1)
V
DDQ
T
A
Supply Voltage
I/O Supply Voltage
Operating Free-Air Temperature
1.7
0
Parameter
Min.
Typ.
V
DDQ
1.8
⎯
1.9
+70
Max.
Unit
V
V
°
C
NOTE:
1. The PLL is turned off and bypassed for test purposes when AV
DD
is grounded. During this test mode, V
DDQ
remains within the recommended operating conditions and no timing
parameters are guaranteed.
3
IDTCSPUA877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (VFBGA)
Pin Name
AGND
AV
DD
CLK,
CLK
FBIN,
FBIN
FBOUT,
FBOUT
GND
V
DDQ
OE
OS
Y
[0:9]
Y
[0:9]
NB
Pin Number
G1
H1
E1, F1
E6, F6
G6, H6
B2 - B5, C2, C5, H2, H5, J2 - J5
D2 - D4, E2, E5, F2, G2 - G5
F5
D5
A3, A4, B1, B6, C1, C6, K1, K2, K5, K6
A1, A2, A5, A6, D1, D6, J1, J6, K3, K4
1.8V analog supply
Differential clock input with a 10KΩ to 100KΩ pulldown resistor
Feedback differential clock input
Feedback differential clock output
Ground
1.8V supply
Output Enable
Output Select (tied to GND or V
DDQ
)
Buffered output of input clock,
CLK
Buffered output of input clock, CLK
No Ball
Description
Ground for 1.8V analog supply
PIN DESCRIPTION (VFQFPN)
Pin Name
AGND
AV
DD
CLK,
CLK
FBIN,
FBIN
FBOUT,
FBOUT
GND
V
DDQ
OE
OS
Y
[0:9]
Y
[0:9]
NB
Pin Number
7
8
4, 5
26, 27
24, 25
10
1, 6, 9, 15, 20, 23, 28, 31, 36
22
21
3, 11, 14, 16, 19, 29, 33, 34, 38, 39
2, 12, 13, 17, 18, 30, 32, 35, 37, 40
1.8V analog supply
Differential clock input with a 10KΩ to 100KΩ pulldown resistor
Feedback differential clock input
Feedback differential clock output
Ground
1.8V supply
Output Enable
Output Select (tied to GND or V
DDQ
)
Buffered output of input clock, CLK
Buffered output of input clock,
CLK
No Ball
Description
Ground for 1.8V analog supply
4
IDTCSPUA877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
FUNCTION TABLE
(1,2)
INPUTS
AV
DD
GND
GND
GND
GND
1.8V (nom)
1.8V (nom)
1.8V (nom)
1.8V (nom)
1.8V (nom)
X
OE
H
H
L
L
L
L
H
H
X
X
OS
X
X
H
L
H
L
X
X
X
X
CLK
L
H
L
H
L
H
L
H
L
(3)
OUTPUTS
CLK
H
L
H
L
H
L
H
L
L
(3)
Y
L
H
L(z)
L(z)
Y
7
Active
L(z)
L(z)
Y
7
Active
L
H
L(z)
Y
H
L
L(z)
L(z)
Y
7
Active
L(z)
L(z)
Y
7
Active
H
L
L(z)
FBOUT
L
H
L
H
L
H
L
H
L(z)
FBOUT
H
L
H
L
H
L
H
L
L(z)
Reserved
PLL
OFF
OFF
OFF
OFF
ON
ON
ON
ON
OFF
H
H
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
2. L(z) means the outputs are disabled to a LOW state, meeting the I
ODL
limit in DC Electrical Characteristics table.
3. The device will enter a low power-down mode when CLK and
CLK
are both at logic LOW.
5
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