MOBILE MULTIMEDIA INTERFACE (M
2
I)
Final
VERY LOW POWER 1.8V
Datasheet
16K X 16
IDT70P9268L
SYNCHRONOUS
DUAL-PORT STATIC RAM
Features
◆
◆
◆
◆
True Dual-Ported Memory Cells
–
Allows simultaneous access of the same memory location
◆
High per-port throughput performance
–
Industrial: 800 Mbps
◆
Low-Power Operation
–
Active: 15 mA (typ.)
–
Standby: 2 uA (typ.)
◆
Multiplexed address and data I/Os
◆
◆
◆
◆
Counter enable and repeat features
Full synchronous operation on both ports
Separate upper-byte and lower-byte controls for multiplexed bus
and bus matching compatibility
LVTTL-compatible, single 1.8V (+/- 100mV) power supply
Industrial temperature range (-40C to +85C)
Available in a 100-ball fpBGA (fine pitch BGA)
Green parts available, see ordering information
Block Diagram
A
0L
– A
13L
I/O
0L
– I/O
15L
ADS
L
UB
L
LB
L
CNTEN
L
CNTRPT
L
CLK
L
DATA
0L
– DATA
15L
DATA
0R
– DATA
15R
I/O
0R
– I/O
15R
ADS
R
UB
R
16K x 16
Address/Data
I/O Control
Addr
0L
– Addr
13L
MEMORY
ARRAY
Addr
0R
– Addr
13R
Address/Data
I/O Control
LB
R
CNTEN
R
CNTRPT
R
CLK
R
SPECIAL FUNCTION
SFEN
LOGIC
SF
0
– SF
7
CE
L
OE
L
R/W
L
INT
L
CLK
L
CONTROL
LOGIC
CE
R
OE
R
R/W
R
INT
R
CLK
R
ZZ CONTROL
ZZ
L
ZZ
R
LOGIC
NOTES:
1. This block diagram depicts operation with the address and data signals mux’d on the right port but not on the left port. If each port is set to operate with the address and data signals
mux’d, then both sides of the block diagram will be the same as the right port pictured above.
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©2007
Integrated Device Technology, Inc.
August 22, 2007
DSC 5695/1
Device Description
Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M
2
I) Dual Port Static RAM
IDT70P9268L
Final Datasheet
Industrial Temperature Range
Designed primarily for use as a high-speed, low-power inter-connect in multi-processor wireless handsets, the IDT70P9268 or Mobile Multimedia
Interconnect (M
2
I) provides many advantages over embedded serial interfaces, asynchronous memories, and other legacy solutions to inter-
processor communication.
Performance
The M
2
I supports unparalleled data throughput rates of up to 900 Mbps per port. This is achieved through the implementation of a synchronous archi-
tecture which allows the device to support much shorter cycle times (20 ns compared to 55 ns for most low-power asynchronous memories). Addition-
ally, the adoption of a synchronous architecture allows the M
2
I to support on-chip counter functionality which helps to eliminate the inefficiencies
associated with asynchronous implementations of the address-data-multiplex (ADM) interface. Asynchronous ADM (address-data multiplex) inter-
faces require the assertion of an external address on one cycle followed by the associated data on the subsequent cycle. This results in an access
scheme that imparts a 50% inefficiency into a system already limited by slow cycle times. The M
2
I’s counter functionality allows a single external
address to be asserted on one cycle followed by data being burst into or out of the device on every subsequent cycle. This, when combined with the
dramatically improved cycle time, translates to roughly six times greater throughput per-port when compared with asynchronous ADM devices.
Power Consumption
In portable applications, power consumption is of vital concern. This is why the M
2
I includes several features targeted at reducing the power consump-
tion of the device itself and the system as a whole. First, the M
2
I was designed to consume 40% less operating current than low-power asynchronous
memories (15 mA compared to 25 mA). When combined with it’s superior performance and counter functionality, which allow it to complete media
transfers in fewer cycles, this enables the M
2
I to consume nearly 90% less energy than asynchronous memories during transfers of a given file size.
Second, the M
2
I features port-specific chip-enable and sleep mode pins which allow the two ports of the M
2
I to be powered down into standby mode
independently of one another. When combined with the M
2
I’s interrupt flag functionality, this allows the processor subsystems to communicate with
one another and to shut off whole portions of the handset which are not in use, dramatically reducing the power consumption of the system.
Flexibility
To help meet the ever changing requirements of wireless handsets, the M
2
I has been designed to provide a great deal of flexibility. The M
2
I has the
ability to support both ADM and traditional SRAM interfaces, allowing it to seamlessly interface with both current and legacy processors. Additionally,
the M
2
I helps to free up GPIO pins on the processors, allowing designers to include differentiating functionality that helps set their product apart from
the competition. By supporting the ADM interface, the M
2
I consumes nearly 50% fewer pins per-port than non-multiplexed solutions. The M
2
I also
frees up additional GPIO pins on the processors by including 8 dynamically programmable GPIO extender pins. These pins allow the processors to
offload the need to monitor or control simple, binary state devices (e.g. switches, LED drivers, etc.) to the M
2
I and allow the processors to use their
GPIO pins for more value added functions.
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August 22, 2007
Pin Configuration
Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M
2
I) Dual Port Static RAM
IDT70P9268L
Final Datasheet
Industrial Temperature Range
IDT70P9268
BY100
100-BALL fpBGA
A1
V
SS
A2
I/O
0
R
A3
V
DD
A4
I/O
4
R
A5
I/O
7
R
A6
V
DD
A7
I/O
10
R
A8
V
DD
A9
I/O
15
R
A10
SFEN
B1
R/W
R
B2
CLK
R
B3
I/O
1
R
B4
V
SS
B5
I/O
5
R
B6
V
SS
B7
I/O
11
R
B8
V
SS
B9
I/O
14
R
B10
OE
R
C1
ADS
R
C2
CNTEN
R
C3
CNTRPT
R
C4
I/O
2
R
C5
I/O
6
R
C6
I/O
8
R
C7
I/O
12
R
C8
ZZ
R
C9
SF
7
C10
V
SS
D1
CE
R
D2
INT
R
D3
UB
R
D4
LB
R
D5
I/O
3
R
D6
I/O
9
R
D7
I/O
13
R
D8
SF
6
D9
SF
5
D10
SF
4
E1
INT
L
E2
V
SS
E3
V
DD
E4
UB
L
E5
CNTRPT
L
E6
SF
0
E7
MSEL
(2)
E8
V
DD
E9
V
SS
E10
V
DD
F1
CE
L
F2
LB
L
F3
CNTEN
L
F4
CLK
L
F5
V
SS
F6
A
13
L
(3)
F7
SF
2
F8
V
SS
F9
V
SS
F10
SF
1
G1
ADS
L
G2
A
0
L(3)
G3
A
3
L
(3)
G4
V
DD
G5
I/O
8
L
G6
I/O
12
L
G7
A
7
L(3)
G8
ZZ
L
G9
OE
L
G10
SF
3
H1
R/W
L
H2
A
2
L(3)
H3
I/O
0
L
H4
V
SS
H5
I/O
4
L
H6
I/O
11
L
H7
I/O
13
L
H8
A
9
L(3)
H9
A
12
L(3)
H10
NC
J1
A
1
L
(3)
J2
A
5
L(3)
J3
I/O
1
L
J4
I/O
6
L
J5
I/O
7
L
J6
I/O
9
L
J7
V
DD
J8
I/O
15
L
J9
A
10
L(3)
J10
A
11
L(3)
K1
A
4
L(3)
K2
A
6
L(3)
K3
I/O
2
L
K4
I/O
3
L
K5
I/O
5
L
K6
V
DD
K7
I/O
10
L
K8
V
SS
K9
I/O
14
L
K10
A
8
L(3)
NOTES:
1. The device setup shown above features multiplexed address and data signals on the right port and non-multiplexed address and data signals on the left port.
2. For multiplexed address and data signal operation on the left port, this pin should be set to V
DD
. For non-multiplexed address and data signal operation on the left port,
this pin should be set to V
SS
.
3. For multiplexed address and data signal operation on the left port, these pins should be set to V
SS
.
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August 22, 2007
Pin Names (70P9268)
Left Port
CE
L
R/W
L
OE
L
A
0L
– A
15L
I/O
0L
– I/O
15L
N/A
CLK
L
UB
L
LB
L
ADS
L
CNTEN
L
CNTRPT
L
INT
L
ZZ
L
Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M
2
I) Dual Port Static RAM
Right Port
CE
R
R/W
R
OE
R
N/A
N/A
I/O+A
0R
– I/O+A
15R
CLK
R
UB
R
LB
R
ADS
R
CNTEN
R
CNTRPT
R
INT
R
ZZ
R
SFEN
SF
0-7
M
SEL
V
DD
V
SS
Names
Chip Enable (Input)
Read/W rite Enable (Input)
Output Enable (Input)
Address (Input)
Data (Input/Output)
Multiplexed Address and Data (Input/Output)
Clock (Input)
Upper Byte Enable (Input)
Lower Byte Enable (Input)
Address Strobe Enable (Input)
Counter Enable (Input)
Counter Repeat (Input)
Interrupt Flag (Output)
Sleep Mode Enable (Input)
Special Function Enable (Input)
Special Function I/O (Input/Output)
Left Port Mode Select
Power (1.8V)
Ground (0V)
IDT70P9268L
Final Datasheet
Industrial Temperature Range
NOTES:
1. The device setup shown above features multiplexed address and data signals on both ports.
2. For non-multiplexed address and data signal operation on the left port, set pin E7 = V
SS
.
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August 22, 2007
Truth Table I - Read/Write and Enable Control (Multiplexed Port)
OE
X
X
X
X
X
X
X
X
H
L
H
L
H
L
H
X
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
X
CE
H
L
L
X
L
X
L
X
L
X
L
X
L
X
L
X
UB
X
H
L
X
H
X
L
X
L
X
H
X
L
X
L
X
LB
X
H
H
X
L
X
L
X
H
X
L
X
L
X
L
X
R/W
X
X
L
L
L
L
L
L
H
H
H
H
H
H
X
X
ADS
X
X
L
H
L
H
L
H
L
H
L
H
L
H
H
X
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
Upper
Byte
High Z
High Z
--
D
IN
--
High Z
--
D
IN
--
D
O UT
--
High Z
--
D
O UT
High Z
High Z
Lower
Byte
High Z
High Z
--
High Z
--
D
IN
--
D
IN
--
High Z
--
D
O UT
--
D
O UT
High Z
High Z
Cycle
X
X
N
N+1
N
N+1
N
N+1
N
N+2
N
N+2
N
N+2
X
X
Address
X
X
A
N
--
A
N
--
A
N
--
A
N
--
A
N
--
A
N
--
X
X
Mode
Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M
2
I) Dual Port Static RAM
IDT70P9268L
Final Datasheet
Industrial Temperature Range
Deslected
Both bytes deselected
W rite to Upper Byte
W rite to Lower Byte
W rite to Both Bytes
Read Upper Byte O nly
Read Lower Byte O nly
Read Both Bytes
Outputs Disabled
Sleep Mode – Power down
Truth Table II - Read/Write and Enable Control (Non-Multiplexed Port)
OE
X
X
X
X
X
L
L
L
H
X
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
X
CE
H
L
L
L
L
L
L
L
L
X
UB
X
H
L
H
L
L
H
L
L
X
LB
X
H
H
L
L
H
L
L
L
X
R/W
X
X
L
L
L
H
H
H
X
X
ZZ
L
L
L
L
L
L
L
L
L
H
Upper Byte I/O
High Z
High Z
D
IN
High Z
D
IN
D
OUT
High Z
D
OUT
High Z
High Z
Lower Byte I/O
High Z
High Z
High Z
D
IN
D
IN
High Z
D
OUT
D
OUT
High Z
High Z
Mode
Deselected
Both Bytes Deselected
W rite To Upper Byte Only
W rite to Lower Byte Only
W rite to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
Sleep Mode – Power Down
Truth Table III - Address Counter Control
External
Address
A
n
X
X
X
Previous
Internal
Address
X
A
n
A
n + 1
X
Internal
Address
Used
A
n
A
n + 1
A
n + 1
A
n
CLK
↑
↑
↑
↑
ADS
CNTEN
CNTRPT
Mode
L
H
H
X
X
L
H
X
H
H
H
L
External Address Used
Counter Enabled – Internal Address
Generation
External Address Blocked – Counter
Disabled (A
n + 1
reused)
Counter Reset to Last External Address
Loaded
Recommended Operating Temperature and Supply Voltage
G ra d e
I n d u s t r ia l
A m b ie n t T e m p e ra tu re
-4 0
°
C to + 8 5
°
C
GND
0V
VDD
1 .8 V + /- 1 0 0 m V
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August 22, 2007
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