Product Specification
PE4309
Product Description
This product is a high linearity, 6-bit RF Digital Step Attenuator
(DSA) covering a 31.5 dB attenuation range in 0.5 dB steps.
The Peregrine 50Ω RF DSA provides a parallel CMOS control
interface and it operates on 3-volt to 5-volt supply. It maintains
high attenuation accuracy over frequency and temperature and
exhibits very low insertion loss and low power consumption.
This Peregrine DSA is available in a 4x4 mm 24 lead QFN
footprint with an exposed ground paddle.
The PE4309 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Schematic Diagram
50
Ω
RF Digital Attenuator
6-bit, 31.5 dB, DC-4.0 GHz
Features
•
Best in class 2.0 kV HBM ESD tolerance
•
Low Insertion Loss: 1.6 dB typical
•
Attenuation: 0.5 dB steps to 31.5 dB
•
High Linearity: Typical 52 dB IP3
•
Best in Class Attenuation accuracy
•
Parallel programming interface
•
Single supply, 3V to 5V operation
•
Standard 3V or 5V CMOS control logic
independent of supply voltage
•
Very low power consumption
•
RoHS-compliant 24-lead 4x4 mm QFN
Figure 2. Package Type
4x4 mm 24-Lead QFN
Switched Attenuator Array
RF Input
Parallel Control
6
Control Logic Interface
Table 1. Electrical Specifications @ +25°C, V
DD
= 3.0 V - 5.0 V
Parameter
Test Conditions
4
Frequency
Min
DC
-
-
-
-
-
-
-
BS
C
O
IT
Typ
1.6
2.2
-
-
0.15
0.7
1.2
32
32
52
45
20
20
-
DC - 2.2 GHz
2.2 - 4.0 GHz
LE
H
PE
T
RF Output
43
12
Maximum
4000
2
3.4
-
-
-
-
-
-
1
E
Units
MHz
dB
dB
dB
dB
dB
dB
dB
dBm
dBm
dBm
dBm
dB
dB
µs
Operation Frequency
Insertion Loss
O
1 dB Compression
2
Input IP3
1
Return Loss
Switching Speed
E
Attenuation Accuracy
Any Bit or Bit Combination
Any Bit or Bit Combination
0.5 - 7.5 dB States
3
8.0 - 15.5 dB States
3
16.0 - 31.5 dB States
3
DC
≤
1.0 GHz
1.0 < 2.2 GHz
2.2 < 3.8 GHz
2.2 < 3.8 GHz
2.2 < 3.8 GHz
W
±(0.10 + 3% of atten setting), not to exceed +0.20 dB
±(0.15 + 3% of atten setting)
-
-
-
1 MHz - 2.2 GHz
2.2 - 4.0 GHz
1 MHz - 2.2 GHz
2.2 - 4.0 GHz
30
-
-
-
15
10
-
EP
LA
Two-tone inputs +18 dBm
DC - 2.2 GHz
2.2 - 4.0 GHz
50% of control voltage to
90% of final attenuation level
Document No. 70-0218-07
│
www.psemi.com
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Notes: 1.
2.
3.
4.
Device Linearity will begin to degrade below 5 MHz.
Note Absolute Maximum in Table 4.
See Figures 12 and 13 for typical attenuation error.
Measurements made in a 50 ohm system (see Figure 4, Test Circuit Block Diagram). Resistors (R2, R3, R5, R6, R7) with a
value of 10K-ohm are used to decouple the RF path from the control inputs.
©2007 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 9
PE4309
Product Specification
Figure 3. Pin Configuration (Top View)
C 0.5
C16
C2
C4
C1
C8
24
23
22
21
Table 3. Operating Ranges
Parameter
V
DD
Power Supply Voltage
I
DD
Power Supply Current
P
IN
Input power (50Ω)
Min
3.0
Typ
3.3
100
Max
5.5
250
+24
Units
V
µA
dBm
20
N/C
VDD
N/C
RF1
N/C
ACG
19
1
2
3
4
5
6
11
10
12
7
8
9
Exposed
Ground
Paddle
18
17
16
15
14
13
N/C
N/C
N/C
RF2
N/C
ACG
Table 4. Absolute Maximum Ratings
Symbol
V
DD
V
I
T
ST
T
OP
P
IN
Parameter/Conditions
Power supply voltage
Voltage on any DC input
Min
-0.3
-0.3
-65
Max
6.0
6.0
Units
V
V
°C
°C
dBm
V
E
Storage temperature range
Operating temperature
range
Input power (50Ω)
-40
ESD voltage (Human Body
Model)
ACG
ACG
ACG
ACG
ACG
N/C
150
85
30
Table 2. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
N/C
7
No Connect
Power supply pin
No Connect
RF port
No Connect
AC Ground connection
AC Ground connection
AC Ground connection
AC Ground connection
AC Ground connection
AC Ground connection
No Connect
No Connect
RF port
No Connect
No Connect
No Connect
AC Ground connection
V
ESD
V
DD
N/C
5
RF1
N/C
5
ACG
6
ACG
ACG
ACG
N/C
N/C
6
Electrostatic Discharge (ESD) Precautions
ACG
6
6
ACG
6
6
7
BS
C
5
ACG
6
RF2
W
N/C
5
N/C
5
N/C
5
C16
C8
C4
C2
C1
O
IT
E
C16
1
1
1
1
1
1
0
0
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rate specified in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Switching Frequency
The PE4309 has a maximum 25 kHz switching rate.
Table 5. Control Voltage
State
Low
High
Attenuation control bit, 16 dB
Attenuation control bit, 8 dB
Attenuation control bit, 4 dB
Attenuation control bit, 2 dB
Attenuation control bit, 1 dB
O
The standard 3V or 5V CMOS control logic is
independent of supply voltage.
EP
LA
C0.5
Attenuation control bit, 0.5 dB
Ground for proper operation
Paddle
GND
Table 6. Truth Table
C8
1
1
1
1
1
0
1
0
Notes: 5. For improved RF performance these No Connect pins can
be connected to RF ground.
6. Pins can either be grounded directly or through coupling
capacitors
7. Pin can either be grounded or No Connect
C4
1
1
1
1
0
1
1
0
Exposed Solder Pad Connection
R
The exposed solder pad on the bottom of the package
must be grounded for proper device operation.
©2007 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 9
Document No. 70-0218-07
43
12
2000
Pin Name
Description
LE
H
PE
T
C2
1
1
1
0
1
1
1
0
Bias Condition
0 to +1.0 Vdc at 2
µA
(typ)
+2.0 to +5 Vdc at 10
µA
(typ)
C1
1
1
0
1
1
1
1
0
C0.5 Attenuation State
1
0
1
1
1
1
1
0
Reference Loss (IL)
0.5 dB
1 dB
2 dB
4 dB
8 dB
16 dB
31.5 dB
│
UltraCMOS™ RFIC Solutions
PE4309
Product Specification
Figure 4. Test Circuit Block Diagram
Peregrine Specification 102-0371
J1
CWN-350-14-0000
14
12
10
8
6
4
2
GND
GND
GND
GND
GND
GND
GND
DB7
DB6
DB5
DB4
DB3
DB2
DB1
13
11
9
7
5
3
1
C16
C8
C4
C1
C0.5
10K
10K
10K
10K
10K
R2
R3
R5
R6
R7
VDD
C1
0.1µF
C2
100pF
R1
0 OHM
23
22
21
24
20
C1
C2
C4
C8
1
2
3
4
5
6
C0.5
C16
19
R8
R4
DNI
J2
SMASM
1
LE
H
PE
T
NC
NC
NC
NC
18
17
16
VDD
NC
RF1
NC
U1
MLPQ4X4_24L
RF2
15
C4
100pF
NC
14
ACG
ACG
13
10K
VDD
43
12
Z=50 Ohm
1
J3
SMASM
Z=50 Ohm
C3
100pF
O
IT
ACG
ACG
ACG
ACG
ACG
7
8
9
10
11
2
E
©2007 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 9
2
C2
Document No. 70-0218-07
│
www.psemi.com
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EP
LA
O
BS
C
E
W
ECT BP050-0024UJ03 4x4
MLP 24 Ld Socket
12
NC
PE4309
Product Specification
Evaluation Kit
The Digital Attenuator Evaluation Kit board was
designed to ease customer evaluation of the
PE4309 Digital Step Attenuator. Connect J2 by
mini clip to Vdd to power the IC. Connect J8 by
mini clip to power the evaluation board support
circuits. The control bits for the six parallel data
inputs (C0.5 to C16) are controlled using S2-S7 to
select bits or bit combinations. This allows any
attenuation setting to be specified as shown in
Table 6.
The de-embed trace (J6 to J7) estimates the PCB
insertion loss for removal from the evaluation
board measurement data.
To evaluate using customer software, J1 can be
installed using a standard 0.100 IDC header
(some circuit modification required, see
schematic).
Figure 5. Evaluation Board Layout
Peregrine Specification 101/0299
R
EP
LA
O
BS
C
E
W
O
IT
The ability to supply different voltages for the
Control circuitry (using J8) and IC Vdd (using J2)
circuits allows for evaluation of circuits using
different control vs. supply voltages.
©2007 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 9
LE
H
PE
T
Document No. 70-0218-07
Figure 6. Evaluation Board Schematic
Peregrine Specification 102/0366
43
12
│
UltraCMOS™ RFIC Solutions
E
PE4309
Product Specification
Typical Performance Data
Figure 7. Insertion Loss, V
dd
= 3.0 V
Figure 8. Attenuation at Major Steps
31.5 dB
LE
H
PE
T
8 dB
4 dB
0 dB
16 dB
31.5 dB
E
16 dB
2 dB
1 dB
0.5 dB
0 dB
16 dB
Document No. 70-0218-07
│
www.psemi.com
R
EP
LA
O
31.5 dB
BS
C
E
W
O
IT
Figure 9. Input Return Loss at Major
Attenuation Steps
Figure 10. Output Return Loss at Major
Attenuation Steps
©2007 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 9
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PCB设计
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