19-4800; Rev 0; 3/00
3.3V, 622Mbps LVDS,
Dual 4:2 Crosspoint Switch
General Description
The MAX3640 is a dual-path crosspoint switch for use
at OC-12 data rates. The MAX3640 can be used to
receive and transmit 622Mbps low-voltage differential
signals (LVDS) across a backplane with minimum jitter
accumulation. Each path incorporates input buffers,
multiplexers, a crosspoint switch, and output drivers.
The four output channels have a redundant set of out-
puts for test or fanning purposes. The device offers sig-
nal-path redundancy for critical data streams.
The MAX3640 has a unique power-saving feature.
When a set of four output channels has been de-select-
ed, the output drivers are powered down to reduce
power consumption by 165mW. The fully differential
architecture ensures low crosstalk, jitter accumulation,
and signal skew.
The MAX3640 is available in a 48-pin TQFP package
and operates from a +3.3V supply over the 0°C to
+85°C temperature range.
o
Single +3.3V Supply
o
257mW Power Consumption (four output
channels enabled)
o
2.8ps
RMS
Output Random Jitter
o
42ps Output Deterministic Jitter
o
Power-Down Feature for Deselected Outputs
o
110ps Channel-to-Channel Skew
o
240ps Output Edge Speed
o
LVDS Inputs/Outputs
o
LVDS Output 3-State Enable
Features
MAX3640
Applications
SONET/SDH Backplanes
High-Speed Parallel Links
Digital Cross-Connects
System Interconnects
ATM Switch Cores
PART
MAX3640UCM
Ordering Information
TEMP. RANGE
0°C to +85°C
PIN-PACKAGE
48 TQFP
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
MAX3869
LASER DRIVER
OPTICAL
TRANSCEIVER
2.5Gbps
MAX3831
4-CHANNEL
INTERCONNECT
MUX/DEMUX
622Mbps
SONET
SOURCE A
MAX3640
CROSSPOINT
SWITCH
SONET
SOURCE B
622Mbps
MAX3866
TIA AND LA
MAX3876
CDR
PARALLEL DATA
OUTPUT
________________________________________________________________
Maxim Integrated Products
1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
3.3V, 622Mbps LVDS,
Dual 4:2 Crosspoint Switch
MAX3640
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC
................................................-0.5V to 5.0V
Input Voltage (LVDS, TTL)..........................-0.5V to (V
CC
+ 0.5V)
Output Voltage (LVDS) ...............................-0.5V to (V
CC
+ 0.5V)
Continuous Power Dissipation (T
A
= +85°C)
48-Pin TQFP (derate 12.5mW/°C) .................................813mW
Operating Temperature Range...............................0°C to +85°C
Storage Temperature Range ............................ -55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to 3.6V, LVDS differential load = 100Ω ±1%, T
A
= 0°C to +85°C. Typical values are at V
CC
= +3.3V, T
A
= +25°C,
unless otherwise noted.)
PARAMETER
Supply Current
LVDS INPUTS AND OUTPUTS
Input Voltage Range
Differential Input Threshold
Threshold Hysteresis
Differential Input Impedance
Input Common-Mode Current
Output Voltage High
Output Voltage Low
Output Voltage Swing
Change in Magnitude of
Differential Output for
Complementary States
Offset Output Voltage
Change in Magnitude of
Output Offset Voltage for
Complementary States
Differential Output Impedance
Output Current
TTL INPUTS
Input Voltage High
Input Voltage Low
Input Current High
Input Current Low
V
IH
V
IL
I
IH
I
IL
V
IH
= 2.0V
V
IL
= 0.8V
-250
-550
2.0
0.8
V
V
µA
µA
V
IN
V
IDTH
V
HYST
R
IN
I
OS
V
OH
V
OL
|V
OD
|
|∆V
OD
|
V
OS
|∆V
OS
|
ENA, ENB = GND
ENA, ENB = V
CC
Shorted together
80
1
120
12
Figure 1
1.125
LVDS input, V
OS
= 1.2V
Figure 1
Figure 1
Figure 1
0.925
250
400
25
1.275
25
85
0
-100
90
100
245
1.475
115
2400
100
mV
mV
mV
Ω
µA
V
V
mV
mV
mV
mV
MΩ
Ω
mA
SYMBOL
I
CC
CONDITIONS
Eight outputs enabled
Four outputs enabled
MIN
TYP
130
78
MAX
175
UNITS
mA
2
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3.3V, 622Mbps LVDS,
Dual 4:2 Crosspoint Switch
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to 3.6V, LVDS differential load = 100Ω ±1%, T
A
= 0°C to +85°C. Typical values are at V
CC
= +3.3V, T
A
= +25°C,
unless otherwise noted.) (Note 1)
PARAMETER
Parallel Input/Output Data Rate
Output Rise/Fall Time
Output Random Jitter
Output Deterministic Jitter
LVDS Output Differential Skew
LVDS Output Channel-to-
Channel Skew
LVDS Output Enable Time
LVDS Output Disable Time
LVDS Propagation Delay from
Input to Output
t
D
t
r
, t
f
RJ
DJ
t
SKEW1
t
SKEW2
266
66
2.5
(Note 2)
20% to 80%
150
SYMBOL
CONDITIONS
MIN
TYP
622
240
2.8
42
24
350
4
200
50
110
MAX
UNITS
Mbps
ps
ps
RMS
ps
ps
ps
ns
ns
ns
MAX3640
Note 1:
AC characteristics are guaranteed by design and characterization.
Note 2:
Deterministic jitter (DJ) is the arithmetic sum of pattern-dependent jitter and pulse-width distortion. DJ is measured while
applying 100mVp-p noise (f
≤
2MHz) to the power supply.
V
OH
LVDS+
SINGLE ENDED
125mV MIN
200mV MAX
V
OS
= 1.2V ±75mV
250mV MIN
400mV MAX
V
OL
V
OH
250mV MIN
400mV MAX
V
OL
V
OS
= 1.2V ±75mV
LVDS-
SINGLE ENDED
125mV MIN
200mV MAX
V
OD
250mV MIN
400mV MAX
0
(LVDS+) - (LVDS-)
DIFFERENTIAL OUTPUT
VOLTAGE
500mV MIN
800mV MAX
Figure 1. LVDS Output Levels
_______________________________________________________________________________________
3
3.3V, 622Mbps LVDS,
Dual 4:2 Crosspoint Switch
MAX3640
Typical Operating Characteristics
(V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
DIFFERENTIAL OUTPUT VOLTAGE
vs. TEMPERATURE
MAX3640 toc01
SUPPLY CURRENT vs. TEMPERATURE
150
140
130
SUPPLY CURRENT (mA)
120
110
100
90
80
70
60
50
0
10
20
30
40
50
60
70
80
TEMPERATURE (°C)
4 OUTPUTS ENABLED
8 OUTPUTS ENABLED
640
DIFFERENTIAL OUTPUT VOLTAGE (mVp-p)
630
620
610
600
590
580
570
560
0
20
40
TEMPERATURE (°C)
60
80
622Mbps EYE DIAGRAM
MAX3640 toc03
1.25Gbps EYE DIAGRAM
INPUT = 2
13
- 1 PRBS
CONTAINS 100 ZEROS
MAX3640 toc04
INPUT = 2
13
- 1 PRBS
CONTAINS 100 ZEROS
100mV/div
100mV/div
200ps/div
100ps/div
4
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MAX3640 toc02
3.3V, 622Mbps LVDS,
Dual 4:2 Crosspoint Switch
MAX3640
Pin Description
PIN
1, 12, 25, 36,
41
2, 11, 26, 35
3, 5, 45, 47
4, 6, 46, 48
7, 9, 13, 15
8, 10, 14, 16
17–20
21, 23, 27, 29
22, 24, 28, 30
31, 33, 37, 39
32, 34, 38, 40
42
43
44
NAME
V
CC
GND
DIA3+, DIA4+, DIA1+,
DIA2+
DIA3-, DIA4-, DIA1-,
DIA2-
DIB1+, DIB2+, DIB3+,
DIB4+
DIB1-, DIB2-, DIB3-,
DIB4-
SEL1–SEL4
DOB4-, DOB3-, DOB2-,
DOB1-
DOB4+, DOB3+,
DOB2+, DOB1+
DOA4-, DOA3-, DOA2-,
DOA1-
DOA4+, DOA3+,
DOA2+, DOA1+
ENB
ENA
IN_SEL
Positive Supply Voltage
Supply Ground
Positive LVDS, Channel-A Data Input
Negative LVDS, Channel-A Data Input
Positive LVDS, Channel-B Data Input
Negative LVDS, Channel-B Data Input
Crosspoint Switch Select, TTL Input. (Table 1)
Negative LVDS, Channel-B Data Output
Positive LVDS, Channel-B Data Output
Negative LVDS, Channel-A Data Output
Positive LVDS, Channel-A Data Output
Channel-B Output Enable, TTL Input. ENB = high enables DOB1−DOB4.
ENB = low powers down DOB1−DOB4 and sets them to a high-impedance state.
Channel-A Output Enable, TTL Input. ENA = high enables DOA1−DOA4.
ENA = low powers down DOA1−DOA4 and sets them to a high-impedance state.
Input Select Pin, TTL Input. Connect to logic high (or V
CC
) to select DIA1−DIA4.
Connect to logic low (or GND) to select DIB1−DIB4.
FUNCTION
Detailed Description
Figure 2 shows the MAX3640’s architecture. It consists
of two data paths; each data path begins with four dif-
ferential input buffers. The IN_SEL pin selects whether
the A or B channels are passed to the 2x2 crosspoint
switch that follows. The SEL_ pins control the routing of
the crosspoint switch. Each crosspoint switch output
drives a pair of LVDS output drivers. This provides a
redundant set of outputs that can be used for fan-out
or test purposes. Each set of outputs, DOA_ and
DOB_, is enabled or disabled by the ENA and ENB
pins. See Table 1 for routing controls.
LVDS Inputs and Outputs
The MAX3640 features LVDS inputs and outputs for
interfacing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifica-
tion. This technology uses 500mV to 800mV differential
low-voltage swings to achieve fast transition times, low
power dissipation, and improved noise immunity.
For proper operation, the data outputs require 100Ω dif-
ferential termination between the inverting and nonin-
verting pins. Do not terminate these outputs to ground.
See Figure 1 for LVDS output voltage specifications.
The data inputs are internally terminated with 100Ω dif-
ferential and therefore do not require external termina-
tion.
5
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