CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
4.5
6
Low Level Input
Voltage
V
IL
-
-
2
4.5
6
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
I
I
I
CC
V
CC
or
GND
V
CC
or
GND
V
OL
V
IH
or V
IL
V
OH
V
IH
or V
IL
-0.02
-0.02
-0.02
-
-4
-5.2
0.02
0.02
0.02
4
2
4.5
6
-
4.5
6
2
4.5
6
4.5
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.98
5.48
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
0.26
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.84
5.34
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
0.33
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.7
5.2
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
0.4
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SYMBOL
V
I
(V)
I
O
(mA)
V
CC
(V)
25
o
C
MIN
TYP
MAX
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
MAX
MIN
MAX
UNITS
5.2
-
0
6
6
6
-
-
-
-
-
-
0.26
±0.1
8
-
-
-
0.33
±1
80
-
-
-
0.4
±1
160
V
µA
µA
3
CD54HC85, CD74HC85, CD54HCT85, CD74HCT85
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
HCT TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
NOTE:
2. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
I
I
I
CC
∆I
CC
(Note 2)
V
CC
and
GND
V
CC
or
GND
V
CC
-2.1
V
OL
V
IH
or V
IL
V
IH
V
IL
V
OH
-
-
V
IH
or V
IL
-
-
-0.02
4.5 to
5.5
4.5 to
5.5
4.5
2
-
4.4
-
-
-
-
0.8
-
2
-
4.4
-
0.8
-
2
-
4.4
-
0.8
-
V
V
V
SYMBOL
V
I
(V)
I
O
(mA)
25
o
C
MIN
TYP
MAX
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
MAX
MIN
MAX
UNITS
V
CC
(V)
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0
0
-
5.5
5.5
4.5 to
5.5
-
-
-
-
100
±0.1
8
360
-
-
-
±1
80
450
-
-
-
±1
160
490
µA
µA
µA
HCT Input Loading Table
INPUT
A0-A3, B0-B3 and (A = B) IN
(A > B) IN, (A < B) IN
UNIT LOADS
1.5
1
NOTE: Unit Load is
∆I
CC
limit specified in DC Electrical Table, e.g.
360µA max at 25
o
C.
Switching Specifications
Input t
r
, t
f
= 6ns
TEST
CONDITIONS
25
o
C
V
CC
(V)
2
4.5
C
L
= 15pF
C
L
= 50pF
A
n
, B
n
to (A = B) OUT
t
PLH,
t
PHL
C
L
= 50pF
C
L
= 15pF
C
L
= 50pF
5
6
2
4.5
5
6
MIN
-
-
-
-
-
-
-
-
TYP
-
-
16
-
-
-
14
-
MAX
195
39
-
33
175
35
-
30
-40
o
C TO
85
o
C
MIN
-
-
-
-
-
-
-
-
MAX
245
47
-
42
240
44
-
37
-55
o
C TO
125
o
C
MIN
-
-
-
-
-
-
-
-
MAX
295
59
-
50
265
53
-
45
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
PARAMETER
HC TYPES
Propagation Delay,
A
n
, B
n
to (A > B) OUT,
(A < B) OUT
SYMBOL
t
PLH,
t
PHL
C
L
= 50pF
4
CD54HC85, CD74HC85, CD54HCT85, CD74HCT85
Switching Specifications
Input t
r
, t
f
= 6ns
(Continued)
25
o
C
V
CC
(V)
2
4.5
5
6
2
4.5
C
L
= 15pF
C
L
= 50pF
Power Dissipation Capacitance
(Notes 3, 4)
Output Transition Times
(Figure 1)
C
PD
-
5
6
5
2
4.5
6
Input Capacitance
HCT TYPES
Propagation Delay,
An, Bn to (A > B) OUT,
(A < B) OUT
An, Bn to (A = B) OUT
C
IN
-
-
4.5
5
4.5
5
4.5
5
4.5
5
4.5
5
-
-
MIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP
-
-
11
-
-
-
9
-
24
-
-
-
-
-
15
-
17
-
12
-
13
-
26
-
MAX
140
28
-
24
120
24
-
20
-
75
15
13
10
37
-
40
-
30
-
31
-
15
-
10
-40
o
C TO
85
o
C
MIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX
175
35
-
30
150
30
-
26
-
95
19
16
10
46
-
50
-
38
-
39
-
19
-
10
-55
o
C TO
125
o
C
MIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX
210
42
-
36
180
36
-
31
-
110
22
19
10
56
-
60
-
45
-
47
-
22
-
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
pF
ns
ns
ns
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
PARAMETER
SYMBOL
TEST
CONDITIONS
(A > B) IN, (A < B) IN, (A = B) IN t
PLH,
t
PHL
C
L
= 50pF
to (A > B) OUT, (A < B) OUT
C
L
= 15pF
C
L
= 50pF
(A > B) IN to (A = B) OUT
t
PLH,
t
PHL
C
L
= 50pF
t
TLH
, t
THL
C
L
= 50pF
t
PLH,
t
PHL
C
L
= 50pF
C
L
= 15pF
t
PLH,
t
PHL
C
L
= 50pF
C
L
= 15pF
(A > B) IN, (A < B) IN, (A = B) IN t
PLH,
t
PHL
C
L
= 50pF
to (A > B) OUT, (A < B) OUT
C
L
= 15pF
(A > B) IN to (A = B) OUT
Output Transition Times
(Figure 1)
Power Dissipation Capacitance
(Notes 3, 4)
Input Capacitance
NOTES:
t
PLH,
t
PHL
C
L
= 50pF
C
L
= 15pF
t
TLH
, t
THL
C
L
= 50pF
C
PD
C
IN
-
3. C
PD
is used to determine the dynamic power consumption, per gate/package.
4. P
D
= V
CC2
f
i
(C
PD
+ C
L
) where f
i
= Input Frequency, C
L
= Output Load Capacitance, V
CC
= Supply Voltage.
Test Circuits and Waveforms
t
r
= 6ns
INPUT
90%
50%
10%
t
TLH
90%
50%
10%
t
PHL
t
PLH
t
f
= 6ns
V
CC
INPUT
GND
t
THL
t
r
= 6ns
2.7V
1.3V
0.3V
t
TLH
90%
INVERTING
OUTPUT
t
PHL
t
PLH
1.3V
10%
t
f
= 6ns
3V
GND
t
THL
INVERTING
OUTPUT
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
Xilinx 三态以太网 MAC 核是可参数化内核，特别适于交换机和路由器等网络设备。
The TEMAC core is ideally suited for the development of high density Gigabit Ethernet communications an ......
单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
