74CBTLV3257-Q100
Quad 1-of-2 multiplexer/demultiplexer
Rev. 1 — 4 July 2013
Product data sheet
1. General description
The 74CBTLV3257-Q100 provides a quad 1-of-2 high-speed multiplexer/demultiplexer
with common select (S) and output enable (OE) inputs. The low ON resistance of the
switch allows inputs to be connected to outputs without adding propagation delay or
generating additional ground bounce noise. When pin OE = LOW, one of the two switches
is selected (low-impedance ON-state) with pin S. When pin OE = HIGH, all switches are in
the high-impedance OFF-state, independent of pin S. To ensure the high-impedance
OFF-state during power-up or power-down, OE should be tied to the V
CC
through a
pull-up resistor. The current-sinking capability of the driver determines the minimum value
of the resistor.
Schmitt trigger action at control input, makes the circuit tolerant to slower input rise and
fall times across the entire V
CC
range from 2.3 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Supply voltage range from 2.3 V to 3.6 V
High noise immunity
Complies with JEDEC standard:
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
5
switch connection between two ports
Rail to rail switching on data I/O ports
CMOS low power consumption
Latch-up performance exceeds 250 mA per JESD78B Class I level A
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
NXP Semiconductors
74CBTLV3257-Q100
Quad 1-of-2 multiplexer/demultiplexer
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74CBTLV3257D-Q100
74CBTLV3257DS-Q100
40 C
to +125
C
40 C
to +125
C
SO16
SSOP16
[1]
TSSOP16
Description
plastic small outline package; 16 leads; body
width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 3.9 mm; lead pitch 0.635 mm
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
Version
SOT109-1
SOT519-1
SOT403-1
Type number
74CBTLV3257PW-Q100
40 C
to +125
C
74CBTLV3257BQ-Q100
40 C
to +125
C
DHVQFN16 plastic dual-in-line compatible thermal
SOT763-1
enhanced very thin quad flat package; no leads;
16 terminals; body 2.5
3.5
0.85 mm
[1]
Also known as QSOP16.
4. Functional diagram
4
2
1A
1B1
3
1B2
2A
7
5
2B1
6
2B2
3A
9
11
3B1
10
3B2
4A
12
14
4B1
13
4B2
S
1
OE
15
001aal213
Fig 1.
Logic diagram
74CBTLV3257_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 4 July 2013
2 of 19
NXP Semiconductors
74CBTLV3257-Q100
Quad 1-of-2 multiplexer/demultiplexer
5. Pinning information
5.1 Pinning
(1) This is not a supply pin. The
substrate is attached to this pad
using conductive die attach
material. There is no electrical or
mechanical requirement to
solder this pad. However, if it is
soldered, the solder land should
remain floating or be connected
to GND.
Fig 2.
Pin configuration
SOT109-1 (SO16) and
SOT519-1 (SSOP16)
Fig 3.
Pin configuration
SOT403-1 (TSSOP16)
Fig 4.
Pin configuration
SOT763-1 (DHVQFN16)
5.2 Pin description
Table 2.
Symbol
S
1B1 to 4B1
1B2 to 4B2
1A to 4A
GND
OE
V
CC
Pin description
Pin
1
2, 5, 11, 14
3, 6, 10, 13
4, 7, 9, 12
8
15
16
Description
select input
B1 input/output
B2 input/output
A input/output
ground (0 V)
output enable input (active LOW)
supply voltage
74CBTLV3257_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 4 July 2013
3 of 19
NXP Semiconductors
74CBTLV3257-Q100
Quad 1-of-2 multiplexer/demultiplexer
6. Functional description
Table 3.
Inputs
OE
L
L
H
[1]
Function table
[1]
Function switch
S
L
H
X
nA = nB1
nA = nB2
disconnect nA and nBn
H = HIGH voltage level; L = LOW voltage level.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
SW
I
IK
I
SK
I
SW
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input voltage
switch voltage
input clamping current
switch clamping current
switch current
supply current
ground current
storage temperature
total power dissipation
Conditions
control inputs
enable and disable mode
V
I
<
0.5
V
V
I
<
0.5
V
V
SW
= 0 V to V
CC
[1]
[2]
Min
0.5
0.5
0.5
50
50
-
-
100
65
Max
+4.6
+4.6
V
CC
+ 0.5
-
-
128
+100
-
+150
500
Unit
V
V
V
mA
mA
mA
mA
mA
C
mW
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage rating may be exceeded if the input clamping current ratings are observed.
The switch voltage ratings may be exceeded if switch clamping current ratings are observed
For SSOP16 and TSSOP16 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN16 packages: P
tot
derates linearly with 4.5 mW/K above 60
C.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
SW
T
amb
t/V
[1]
Recommended operating conditions
Parameter
supply voltage
input voltage
switch voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.3 V to 3.6 V
[1]
Conditions
Min
2.3
0
Max
3.6
3.6
V
CC
+125
200
Unit
V
V
V
C
ns/V
enable and disable mode
0
40
0
Applies to control signal levels.
74CBTLV3257_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 4 July 2013
4 of 19
NXP Semiconductors
74CBTLV3257-Q100
Quad 1-of-2 multiplexer/demultiplexer
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
V
IL
I
I
I
S(OFF)
I
S(ON)
I
OFF
I
CC
HIGH-level
input voltage
Conditions
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
T
amb
=
40 C
to +85
C
Min
1.7
2.0
-
-
-
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
-
-
Max
-
-
0.7
0.9
1
1
1
10
10
T
amb
=
40 C
to +125
C
Unit
Min
1.7
2.0
-
-
-
-
-
-
-
Max
-
-
0.7
0.9
20
20
20
50
50
V
V
V
V
A
A
A
A
A
LOW-level input V
CC
= 2.3 V to 2.7 V
voltage
V
CC
= 3.0 V to 3.6 V
input leakage
current
pin OE, S; V
I
= GND to V
CC
;
V
CC
= 3.6 V
OFF-state
V
CC
= 3.6 V; see
Figure 5
leakage current
ON-state
V
CC
= 3.6 V; see
Figure 6
leakage current
power-off
V
I
or V
O
= 0 V to 3.6 V;
leakage current V
CC
= 0 V
supply current
V
I
= GND or V
CC
; I
O
= 0 A;
V
SW
= GND or V
CC
;
V
CC
= 3.6 V
pin OE, S; V
I
= V
CC
0.6 V;
V
SW
= GND or V
CC
;
V
CC
= 3.6 V
pin OE, S; V
CC
= 3.3 V;
V
I
= 0 V to 3.3 V
V
CC
= 3.3 V; V
I
= 0 V to 3.3 V
V
CC
= 3.3 V; V
I
= 0 V to 3.3 V
[2]
I
CC
additional
supply current
input
capacitance
OFF-state
capacitance
ON-state
capacitance
-
-
300
-
2000
A
C
I
C
S(OFF)
C
S(ON)
-
-
-
0.9
5.2
14.3
-
-
-
-
-
-
-
-
-
pF
pF
pF
[1]
[2]
All typical values are measured at T
amb
= 25
C.
One input at 3 V, other inputs at V
CC
or GND.
9.1 Test circuits
V
CC
V
IH
Is
V
CC
V
IL
Is
Is
nOE
nBn
GND
nA
nOE
nA
GND
nBn
VO
A
Vl
A
VO
Vl
A
001aai101
001aai103
V
I
= V
CC
or GND and V
O
= GND or V
CC
.
V
I
= V
CC
or GND and V
O
= open circuit.
Fig 5.
Test circuit for measuring OFF-state leakage
current (one switch)
Fig 6.
Test circuit for measuring ON-state leakage
current (one switch)
74CBTLV3257_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 4 July 2013
5 of 19
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