SN54ABT16952, SN74ABT16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS082C – FEBRUARY 1991 – REVISED JANUARY 1997
D
D
D
D
D
D
D
D
Members of the Texas Instruments
Widebus
™
Family
State-of-the-Art
EPIC-
ΙΙ
B
™
BiCMOS Design
Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical V
OLP
(Output Ground Bounce) < 1 V
at V
CC
= 5 V, T
A
= 25°C
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
High-Drive Outputs (–32-mA I
OH
, 64-mA I
OL
)
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
SN54ABT16952 . . . WD PACKAGE
SN74ABT16952 . . . DGG OR DL PACKAGE
(TOP VIEW)
description
The ’ABT16952 are 16-bit registered transceivers
that contain two sets of D-type flip-flops for
temporary storage of data flowing in either
direction. The ’ABT16952 can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the
A or B bus is stored in the registers on the
low-to-high transition of the clock (CLKAB or
CLKBA) input provided that the clock-enable
(CLKENAB or CLKENBA) input is low. Taking the
output-enable (OEAB or OEBA) input low
accesses the data on either port.
1OEAB
1CLKAB
1CLKENAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2CLKENAB
2CLKAB
2OEAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEBA
1CLKBA
1CLKENBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2CLKENBA
2CLKBA
2OEBA
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16952 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16952 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
Copyright
©
1997, Texas Instruments Incorporated
•
DALLAS, TEXAS 75265
1
SN54ABT16952, SN74ABT16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS082C – FEBRUARY 1991 – REVISED JANUARY 1997
FUNCTION TABLE†
INPUTS
CLKENAB
H
X
L
L
X
CLKAB
X
L
↑
↑
X
OEAB
L
L
L
L
H
A
X
X
L
H
X
OUTPUT
B
B0‡
B0‡
L
H
Z
† A-to-B data flow is shown; B-to-A data flow is similar, but
uses CLKENBA, CLKBA, and OEBA.
‡ Level of B before the indicated steady-state input
conditions were established
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54ABT16952, SN74ABT16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS082C – FEBRUARY 1991 – REVISED JANUARY 1997
logic symbol
†
1OEBA
1CLKENBA
1CLKBA
1OEAB
3
1CLKENAB
1CLKAB
2OEBA
31
2CLKENBA
2CLKBA
2OEAB
2CLKENAB
2CLKAB
1A1
30
28
26
27
5
2
29
56
54
55
1
EN3
G1
1C5
EN4
G2
2C6
EN9
G7
7C11
EN10
G8
8C12
3
6D
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
6
8
9
10
12
13
14
15
9
12D
2A2
2A3
2A4
2A5
2A6
2A7
2A8
16
17
19
20
21
23
24
11D
10
41
40
38
37
36
34
33
2B2
2B3
2B4
2B5
2B6
2B7
2B8
5D
4
52
1B1
51
49
48
47
45
44
43
42
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SN54ABT16952, SN74ABT16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS082C – FEBRUARY 1991 – REVISED JANUARY 1997
logic diagram (positive logic)
1CLKENAB
1CLKAB
1OEBA
3
2
56
54
55
1
1CLKENBA
1CLKBA
1OEAB
1A1
5
One of Eight
Channels
C1
CE
1D
C1
CE
1D
52
1B1
To Seven Other Channels
2CLKENAB
2CLKAB
2OEBA
26
27
29
31
30
28
2CLKENBA
2CLKBA
2OEAB
One of Eight
Channels
2A1
15
C1
CE
1D
C1
CE
1D
42
2B1
To Seven Other Channels
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54ABT16952, SN74ABT16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS082C – FEBRUARY 1991 – REVISED JANUARY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, V
I
(except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, V
O
. . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, I
O
: SN54ABT16952 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT16952 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, I
OK
(V
O
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance,
θ
JA
(see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABT16952
MIN
VCC
VIH
VIL
VI
IOH
IOL
∆t/∆v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Outputs enabled
–55
0
4.5
2
0.8
VCC
–24
48
10
125
–40
0
MAX
5.5
SN74ABT16952
MIN
4.5
2
0.8
VCC
–32
64
10
85
MAX
5.5
UNIT
V
V
V
V
mA
mA
ns/V
°C
TA
Operating free-air temperature
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
