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74F1071 — 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device
January 2008
74F1071
18-Bit Undershoot/Overshoot Clamp and ESD
Protection Device
Features
■
18-bit array structure in 20-pin package
■
FAST
■
■
■
■
General Description
The 74F1071 is an 18-bit undershoot/overshoot clamp
which is designed to limit bus voltages and also to pro-
tect more sensitive devices from electrical overstress
due to electrostatic discharge (ESD). The inputs of the
device aggressively clamp voltage excursions nominally
at 0.5V below and 7V above ground.
Bipolar voltage clamping action
Dual center pin grounds for min inductance
Robust design for ESD protection
Low input capacitance
Optimum voltage clamping for 5V CMOS/TTL
applications
Ordering Information
Order Number
74F1071SC
74F1071MSA
74F1071MTC
Package
Number
M20B
MSA20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Note:
Simplified Component Representation
©1994 Fairchild Semiconductor Corporation
74F1071 Rev. 1.4.0
www.fairchildsemi.com
74F1071 — 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
T
STG
T
A
T
J
V
I
I
I
Storage Temperature
Parameter
Ambient Temperature Under Bias
Junction Temperature Under Bias
Input Voltage
(1)
Input Current
(1)
ESD
(2)
Human Body Model (MIL-STD-883D method 3015.7)
IEC 801-2
Machine Model (EIAJIC-121-1981)
DC Latchup Source Current (JEDEC Method 17)
Package Power Dissipation @ +70°C SOIC Package
Rating
–65°C to +150°C
–65°C to +125°C
–65°C to +150°C
–0.5V to +6V
–200mA to +50mA
±10kV
±6kV
±2kV
±500mA
800mW
Notes:
1. Voltage ratings may be exceeded if current ratings and junction temperature and power consumption ratings are not
exceeded.
2. ESD Rating for Direct contact discharge using ESD Simulation Tester. Higher rating may be realized in the actual
application.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
T
A
V
Z
θ
JA
Free Air Ambient Temperature
Reverse Bias Voltage
Parameter
Rating
0°C to +70°C
0V to 5.25 V
DC
100°C/W
110°C/W
Thermal Resistance (in Free Air)
SOIC Package
SSOP Package
©1994 Fairchild Semiconductor Corporation
74F1071 Rev. 1.4.0
www.fairchildsemi.com
2
74F1071 — 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device
DC Electrical Characteristics
T
A
=
+25°C
Symbol
I
IH
T
A
=
0°C to +70°C
Min.
Max.
50
100
5.9
7.7
8.0
–0.3
–0.5
–0.9
–1.5
%
pF
V
V
Parameter
Input HIGH Current
Conditions
V
IN
=
5.25V; Untested
Input @ GND
V
IN
=
5.5V; Untested
Input @ GND
Min.
Typ.
1.5
3
Max.
10
20
7.2
7.5
–0.9
–1.5
3
Units
µA
V
Z
Reverse Voltage
I
Z
=
1mA; Untested
Inputs @ GND
I
Z
=
50mA; Untested
Inputs @ GND
6.6
6.9
7.1
V
F
Forward Voltage
I
F
=
–18mA; Untested
Inputs @ 5V
I
F
=
–200mA; Untested
Inputs @ 5V
–0.3
–0.5
–0.6
–1.1
I
CT
C
IN
Adjacent Input
Crosstalk
Input Capacitance
V
BIAS
=
0 V
DC
(small signal @ 1MHz) V
BIAS
=
5 V
DC
25
13
©1994 Fairchild Semiconductor Corporation
74F1071 Rev. 1.4.0
www.fairchildsemi.com
3
74F1071 — 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device
DC Electrical Characteristics
Typical Forward and Reverse V/I Characteristics
Typical Reverse Conduction Characteristics
Typical Forward Conduction Characteristics
ESD Network
Human Body Model
IEC 801-2
CZ
100pF
150pF
RZ
1500
Ω
330
Ω
Simulated ESD Voltage Clamping Test Circuit
©1994 Fairchild Semiconductor Corporation
74F1071 Rev. 1.4.0
www.fairchildsemi.com
4
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