Si86xx
1 M
B PS
, 2.5
K
V
RMS
D
IGITAL
I
SOLATORS
Features
High-speed operation
DC to 1 Mbps
No start-up initialization required
Wide Operating Supply Voltage
2.5–5.5 V
Up to 2500 V
RMS
isolation
60-year life at rated working voltage
High electromagnetic immunity
Ultra low power (typical)
5 V Operation
1.6 mA per channel at 1 Mbps
2.5 V Operation
1.5 mA per channel at 1 Mbps
Tri-state outputs with ENABLE
Schmitt trigger inputs
Transient Immunity 50 kV/µs
AEC-Q100 qualification
Wide temperature range
–40 to 125 °C
RoHS-compliant packages
SOIC-16 wide body
SOIC-16 narrow body
SOIC-8 narrow body
Applications
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power inverters
Communication systems
Safety Regulatory Approvals
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
CSA component notice 5A approval
CQC certification approval
IEC 60950-1, 61010-1
GB4943.1
UL 1577 recognized
Up to 2500 V
RMS
for 1 minute
Ordering Information:
See page 38.
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices
offering substantial data rate, propagation delay, power, size, reliability, and
external BOM advantages over legacy isolation technologies. The operating
parameters of these products remain stable across wide temperature ranges
and throughout device service life for ease of design and highly uniform
performance. All device versions have Schmitt trigger inputs for high noise
immunity and only require VDD bypass capacitors.
All products support Data rates up to 1 Mbps and Enable inputs which provide
a single point control for enabling and disabling output drive. All products are
safety certified by UL, CSA, VDE, and CQC and support withstand ratings up
to 2.5 kV
RMS
.
Rev. 0.9 9/13
Copyright © 2013 by Silicon Laboratories
Si86xx
Si86xx
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.2. Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4. Pin Descriptions (Si861x/2x Narrow Body SOIC-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5. Pin Descriptions (Si863x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
6. Pin Descriptions (Si864x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
7. Pin Descriptions (Si8650/51/52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8. Pin Descriptions (Si866x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
11. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
14. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
15. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
16. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
16.1. Top Marking (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
16.2. Top Marking Explanation (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . 48
16.3. Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
16.4. Top Marking Explanation (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . 49
16.5. Top Marking (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
16.6. Top Marking Explanation (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . 50
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Rev. 0.9
3
Si86xx
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating Temperature*
Supply Voltage
Symbol
T
A
V
DD1
V
DD2
Min
–40
2.5
2.5
Typ
25
—
—
Max
125
5.5
5.5
Unit
ºC
V
V
*Note:
The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Electrical Characteristics
(V
DD1
= 5 V±10%, V
DD2
= 5 V±10%, T
A
= –40 to 125 °C)
Parameter
Symbol
VDD Undervoltage
VDDUV+
Threshold
VDD Undervoltage
VDDUV–
Threshold
VDD Undervoltage
VDD
HYS
Hysteresis
Positive-Going Input
VT+
Threshold
Negative-Going
VT–
Input Threshold
Input Hysteresis
V
HYS
High Level Input Voltage
V
IH
Low Level input voltage
V
IL
High Level Output Voltage
V
OH
Low Level Output Voltage
Input Leakage Current
Output Impedance
1
Enable Input High Current
Enable Input Low Current
V
OL
I
L
Z
O
I
ENH
I
ENL
Test Condition
V
DD1
, V
DD2
rising
V
DD1
, V
DD2
falling
Min
1.95
1.88
50
Typ
2.24
2.16
70
1.67
1.23
0.44
—
—
4.8
0.2
—
50
2.0
2.0
Max
2.375
2.325
95
1.9
1.4
0.50
—
0.8
—
0.4
±10
—
—
—
Unit
V
V
mV
V
V
V
V
V
V
V
µA
µA
µA
All inputs rising
All inputs falling
1.4
1.0
0.38
2.0
—
V
DD1
,V
DD2
–
0.4
—
—
—
—
—
loh = –4 mA
lol = 4 mA
V
ENx
= V
IH
V
ENx
= V
IL
Notes:
1.
The nominal output impedance of an isolator driver channel is approximately 50
,
±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2.
t
PSK(P-P)
is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3.
Start-up time is the time period from the application of power to valid data at the output.
4
Rev. 0.9
Si86xx
Table 2. Electrical Characteristics (Continued)
(V
DD1
= 5 V±10%, V
DD2
= 5 V±10%, T
A
= –40 to 125 °C)
Parameter
Si8610Ax
V
DD1
V
DD2
V
DD1
V
DD2
Si8620Ax
V
DD1
V
DD2
V
DD1
V
DD2
Si8621Ax
V
DD1
V
DD2
V
DD1
V
DD2
Si8630Ax
V
DD1
V
DD2
V
DD1
V
DD2
Si8631Ax
V
DD1
V
DD2
V
DD1
V
DD2
Si8640Ax
V
DD1
V
DD2
V
DD1
V
DD2
Si8641Ax
V
DD1
V
DD2
V
DD1
V
DD2
Si8642Ax
V
DD1
V
DD2
V
DD1
V
DD2
Symbol
Test Condition
Min
DC Supply Current
(All inputs 0 V or at Supply)
V
I
= 0(Ax)
V
I
= 0(Ax)
V
I
= 1(Ax)
V
I
= 1(Ax)
V
I
= 0(Ax)
V
I
= 0(Ax)
V
I
= 1(Ax)
V
I
= 1(Ax)
V
I
= 0(Ax)
V
I
= 0(Ax)
V
I
= 1(Ax)
V
I
= 1(Ax)
V
I
= 0(Ax)
V
I
= 0(Ax)
V
I
= 1(Ax)
V
I
= 1(Ax)
V
I
= 0(Ax)
V
I
= 0(Ax)
V
I
= 1(Ax)
V
I
= 1(Ax)
V
I
= 0(Ax)
V
I
= 0(Ax)
V
I
= 1(Ax)
V
I
= 1(Ax)
V
I
= 0(Ax)
V
I
= 0(Ax)
V
I
= 1(Ax)
V
I
= 1(Ax)
V
I
= 0(Ax)
V
I
= 0(Ax)
V
I
= 1(Ax)
V
I
= 1(Ax)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ
Max
Unit
0.6
0.8
1.8
0.8
0.8
1.4
3.3
1.4
1.2
1.2
2.4
2.4
0.9
1.9
4.6
1.9
1.3
1.7
3.9
3.0
1.0
2.4
6.1
2.5
1.4
2.3
5.2
3.6
1.8
1.8
4.4
4.4
1.2
1.5
2.9
1.5
1.4
2.2
5.3
2.2
1.9
1.9
3.8
3.8
1.6
3.0
7.4
3.0
2.1
2.7
5.9
4.5
1.6
3.8
9.2
4.0
2.2
3.7
7.8
5.4
2.9
2.9
6.6
6.6
mA
mA
mA
mA
mA
mA
mA
mA
Notes:
1.
The nominal output impedance of an isolator driver channel is approximately 50
,
±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2.
t
PSK(P-P)
is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3.
Start-up time is the time period from the application of power to valid data at the output.
Rev. 0.9
5
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