PRELIMINARY
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS
FANOUT BUFFER
ICS854S013
General Description
The ICS854S013 is a low skew, high performance
Dual 1-to-3 Differential-to-LVDS Fanout Buffer and
HiPerClockS™
a member of the HiPerClockS™ family of High
Performance Clock Solutions from IDT. The PCLKx,
nPCLKx pairs can accept most standard differential
input levels. The ICS854S013 is characterized to operate from a
3.3V power supply. Guaranteed output and bank skew character-
istics make the ICS854S013 ideal for those clock distribution
applications demanding well defined performance and
repeatability.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Two differential LVDS output banks
Two differential clock input pairs
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: >3GHz
Translates any single ended input signal to LVDS levels with
resistor bias on nPCLKx input
Output skew: <25ps (typical)
Bank skew: <50ps (typical)
Propagation delay: TBD
Additive phase jitter, RMS: 0.15ps (typical)
Full 3.3V power supply
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
ICS
Block Diagram
QA0
nQA0
PCLKA
Pulldown
nPCLKA
Pullup
QA1
nQA1
QA2
nQA2
QB0
nQB0
PCLKB
Pulldown
nPCLKB
Pullup
QB1
nQB1
QB2
nQB2
Pin Assignment
nQA0
QA0
V
DD
PCLKA
nPCLKA
PCLKB
nPCLKB
V
DD
nQB0
QB0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
QA1
nQA1
QA2
nQA2
V
DD
QB2
nQB2
QB1
nQB1
GND
ICS854S013
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm package body
G Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™
LVDS FANOUT BUFFER
1
ICS854S013BG REV. A FEBRUARY 26, 2008
ICS854S013
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
Table 1. Pin Descriptions
Number
1, 2
3, 8, 16
4
5
6
7
9, 10
11
12, 13
14, 15
17, 18
19, 20
Name
nQA0, QA0
V
DD
PCLKA
nPCLKA
PCLKB
nPCLKB
nQB0, QB0
GND
nQB1, QB1
nQB2, QB2
nQA2, QA2
nQA1, QA1
Output
Power
Input
Input
Input
Input
Output
Power
Output
Output
Output
Output
Pulldown
Pullup
Pulldown
Pullup
Type
Description
Differential output pair. LVDS interface levels.
Power supply pins.
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
Differential output pair. LVDS interface levels.
Power supply ground.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
Table 3. Clock Input Function Table
Inputs
PCLKA, PCLKB
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nPCLKA, nPCLKB
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Outputs
QA[0:2], QB[0:2]
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQA[0:2], nQB[0:2]
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single-ended to Differential
Single-ended to Differential
Single-ended to Differential
Single-ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
NOTE 1: Please refer to the Application Information Section,
Wiring the Differential Input to Accept Single-ended Levels.
IDT™ / ICS™
LVDS FANOUT BUFFER
2
ICS854S013BG REV. A FEBRUARY 26, 2008
ICS854S013
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
87.2°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
135
Maximum
3.465
Units
V
mA
Table 4B. LVPECL Differential DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
I
IH
Parameter
PCLKA, PCLKB
Input High Current
nPCLKA, nPCLKB
PCLKA, PCLKB
I
IL
Input Low Current
nPCLKA, nPCLKB
V
PP
V
CMR
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V,
V
IN
= 0V
V
DD
= 3.465V,
V
IN
= 0V
-5
-150
0.15
GND + 0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
IDT™ / ICS™
LVDS FANOUT BUFFER
3
ICS854S013BG REV. A FEBRUARY 26, 2008
ICS854S013
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
Table 4C. LVDS DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
Typical
360
50
1.35
50
Maximum
Units
mV
mV
V
mV
Table 5. AC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Parameter
f
MAX
t
PD
tsk(o)
tsk(b)
tjit
t
R
/ t
F
odc
Symbol
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Bank Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Rise/Fall Time
Output Duty Cycle
100MHz, Integration Range:
12kHz – 20MHz
20% to 80%
TBD
<25
<50
0.15
200
50
ps
%
Test Conditions
Minimum
Typical
Maximum
>3
Units
GHz
ps
ps
ps
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured from the output differential cross points.
NOTE 3: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™
LVDS FANOUT BUFFER
4
ICS854S013BG REV. A FEBRUARY 26, 2008
ICS854S013
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a
dBc
value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
0
-10
-20
-30
-40
-50
SSB Phase Noise dBc/Hz
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
Additive Phase Jitter @ 100MHz
12kHz to 20MHz = 0.15ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
IDT™ / ICS™
LVDS FANOUT BUFFER
5
ICS854S013BG REV. A FEBRUARY 26, 2008
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