®
74LVX174
HEX D-TYPE FLIP FLOP WITH CLEAR
WITH 5V TOLERANT INPUTS
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 180 MHz (TYP.) at V
CC
= 3.3V
5V TOLERANT INPUTS
POWER-DOWN PROTECTION ON INPUTS
INPUT VOLTAGE LEVEL:
V
IL
= 0.8V, V
IH
= 2V at V
CC
= 3V
LOW POWER DISSIPATION:
I
CC
= 4
µA
(MAX.) at T
A
= 25
o
C
LOW NOISE:
V
OLP
= 0.3 V (TYP.) at V
CC
= 3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 174
IMPROVED LATCH-UP IMMUNITY
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVX174M
74LVX174T
Information signals applied to D inputs are
transfered to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independently of the other inputs .
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The LVX174 is a low voltage CMOS HEX
D-TYPE FLIP FLOP WITH CLEAR NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
3.3V applications.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 1999
1/10
74LVX174
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Storage Temperature
Lead Temperature (10 sec)
Parameter
Value
-0.5 to +7.0
-0.5 to 7.0
-0.5 to V
CC
+ 0.5
- 20
±
20
±
25
±
50
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
o
o
I
CC
or I
GND
DC V
CC
or Ground Current
C
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Supply Voltage (note 1)
Input Voltage
Output Voltage
Operating Temperature:
Input Rise and Fall Time (V
CC
= 3V) (note 2)
Parameter
Valu e
2 to 3.6
0 to 5.5
0 to V
CC
-40 to +85
0 to 100
Unit
V
V
V
o
C
ns/V
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2V
3/10
74LVX174
DC SPECIFICATIONS
Symb ol
Parameter
V
CC
(V)
V
IH
High Level Input Voltage
2.0
3.0
3.6
V
IL
Low Level Input Voltage
2.0
3.0
3.6
V
OH
High Level Output Voltage
2.0
3.0
3.0
V
OL
Low Level Output Voltage
2.0
3.0
3.0
I
I
I
CC
Input Leakage Current
Quiescent Supply Current
3.6
3.6
V
I
=
V
IH
or
V
IL
V
I
=
V
IH
or
V
IL
(*)
(* )
Test Co nditions
o
Valu e
T
A
= 25 C
Min.
1.5
2.0
2.4
0.5
0.8
0.8
T yp.
Max.
-40 to 85 C
Min.
1.5
2.0
2.4
0.5
0.8
0.8
1.9
2.9
2.48
0.0
0.0
0.1
0.1
0.36
±0.1
4
0.1
0.1
0.44
±1
40
Max.
o
Un it
V
V
I
O
=-50
µA
I
O
=-50
µA
I
O
=-4 mA
I
O
=50
µ
A
I
O
=50
µA
I
O
=4 mA
1.9
2.9
2.58
2.0
3.0
V
V
µA
µA
V
I
= 5V or GND
V
I
= V
CC
or GND
(*) All outputs loaded.
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol
Parameter
V
CC
(V)
V
OLP
V
OLV
V
IHD
V
ILD
Dynamic Low Voltage
Quiet Output (note 1, 2)
Dynamic High Voltage
Input (note 1, 3)
Dynamic Low Voltage
Input (note 1, 3)
3.3
-0.8
3.3
3.3
C
L
= 50 pF
0.8
Test Co nditions
o
Valu e
T
A
= 25 C
Min.
T yp.
0.3
-0.3
2
Max.
0.8
-40 to 85 C
Min.
Max.
o
Un it
V
1) Worst case package
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND
3) max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold (V
IHD
). f=1MHz
4/10
74LVX174
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
=3 ns)
Symb ol
Parameter
T est Con ditio n
V
CC
C
L
(V)
(p F)
2.7
2.7
3.3
(*)
3.3
(*)
2.7
2.7
3.3
(*)
3.3
(*)
2.7
3.3
2.7
(*)
t
PLH
t
PHL
Propagation Delay Time
CK to Q
15
50
15
50
15
50
15
50
Valu e
T
A
= 25 C
-40 to
Min. T yp. Max. Min.
7.6
14.5
1.0
10.1 18.0
1.0
o
Un it
85 C
Max.
17.5
21.0
11.0
14.5
18.5
22.0
11.5
15.0
7.5
5.0
7.5
5.0
8.5
6.0
0.0
0.0
4.5
3.0
o
ns
t
PLH
t
PHL
Propagation Delay Time
CLR to Q
t
wL
t
w
t
s
t
h
t
REM
f
MAX
CLR pulse Width, HIGH
CK pulse Width
Setup Time Q to CK HIGH
or LOW
Hold Time Q to CK HIGH
or LOW
Recovery Time CLR to Q
Maximum Clock Frequency
5.9
8.4
7.9
10.4
6.2
8.7
6.5
5.0
6.5
5.0
7.5
5.0
0.0
0.0
4.5
3.0
130
60
180
95
0.5
0.5
9.3
12.8
15.0
18.5
9.7
13.2
1.0
1.0
1.0
1.0
1.0
1.0
ns
ns
ns
ns
ns
ns
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
2.7
3.3
(*)
3.3
2.7
3.3
(*)
15
50
15
50
50
50
65
45
115
65
55
40
95
55
1.0
1.0
1.5
1.5
MHz
t
OSLH
t
OSHL
Output to Output Skew
Time (note 1, 2)
ns
(*)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the
same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
±
0.3V
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
V
CC
(V)
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance (note 1)
3.3
3.3
f
IN
= 10 MHz
Test Co nditions
o
Valu e
T
A
= 25 C
Min.
T yp.
5
23
Max.
-40 to 85 C
Min.
Max.
o
Un it
pF
pF
1) C
PD
isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operting current can be obtained by the following equation. I
CC
(opr) = C
PD
•
V
CC
•
f
IN
+ I
CC
/n(per circuit)
5/10
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