19-0810; Rev 0; 4/07
Overvoltage Protectors with
External pFET
General Description
The MAX4923–MAX4926 overvoltage protection
(OVP) controllers protect low-voltage systems against
high-voltage faults of up to +28V with an appropriate
external pFET. When the input voltage exceeds the over-
voltage lockout (OVLO) threshold, or falls below the
undervoltage lockout (UVLO) threshold, these devices
turn off the pFET to prevent damage to protected compo-
nents and issue a flag to notify the processor of a fault
condition.
The typical overvoltage trip level is set to 7.18V
(MAX4923), 6.16V (MAX4924), 5.65V (MAX4925), and
4.46V (MAX4926). The undervoltage trip level is set to
2.44V (typ) for all devices.
The input (IN) is ESD protected to ±15kV HBM when
bypassed to ground with a 1µF ceramic capacitor. All
devices are offered in a small, 6-pin (1.5mm x 1.0mm)
µDFN package and are specified over the extended
-40°C to +85°C temperature range.
o
Overvoltage Protection Up to +28V
o
Preset 7.18V, 6.16V, 5.65V, and 4.46V Typical
Overvoltage Trip Levels
o
Preset 2.44V Typical Undervoltage Trip Level
o
±2.5% Accurate Overvoltage/Undervoltage
Trip Levels
o
Low 13µA (typ) Supply Current
o
Drives External pFET
o
20ms Adapter Debounce Time
o
Fault Flag Indicator
o
6-Pin (1.5mm x 1.0mm) µDFN Package
Features
MAX4923–MAX4926
Applications
Cell Phones
Digital Still Cameras
PDAs and Palmtop Devices
MP3 Players
INPUT
+1.8V TO 28V
Typical Operating Circuit
P
OUTPUT
Pin Configuration
TOP VIEW
N.C
6
N.C
5
GATE
4
1μF
1
IN
4
GATE
MAX4923–MAX4926
V
IO
2
3
GND
FLAG
MA4923
–
MAX4926
1
IN
2
GND
3
FLAG
μDFN
Ordering Information/Selector Guide
PART
MAX4923ELT+*
MAX4924ELT+
MAX4925ELT+
MAX4926ELT+
PIN-PACKAGE
6 μDFN
6 μDFN
6 μDFN
6 μDFN
OVLO (V)
7.18
6.16
5.65
4.46
UVLO (V)
2.44
2.44
2.44
2.44
TOP MARK
LB
LC
LD
LE
PKG CODE
L611-1
L611-1
L611-1
L611-1
Note:
All devices are specified over the -40°C to +85°C operating temperature range.
+Denotes
lead-free package.
*Future
Product—contact factory for availability.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Overvoltage Protectors with
External pFET
MAX4923–MAX4926
ABSOLUTE MAXIMUM RATINGS
IN, GATE to GND....................................................-0.3V to +30V
FLAG to GND ...........................................................-0.3V to +6V
Continuous Power Dissipation (T
A
= +70°C)
6-µDFN (derate 2.1mW/°C above 70°C) .......................168mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300 °C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
IN
= +5V for MAX4923/MAX4924/MAX4925, V
IN
= +4V for MAX4926, C
GATE
= 500pF to IN, T
A
= -40°C to +85°C, unless otherwise
noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
Input Voltage Range
SYMBOL
V
IN
MAX4923
Overvoltage Lockout Level
OVLO
V
IN
rising
MAX4924
MAX4925
MAX4926
MAX4923
Overvoltage Lockout Hysteresis
MAX4924
MAX4925
MAX4926
Undervoltage Lockout Level
Undervoltage Lockout Hysteresis
IN Supply Current
GATE Voltage High
GATE Pulldown Current
FLAG Low Voltage
FLAG Leakage Current
TIMING CHARACTERISTICS
Debounce Time
t
DEB
V
UVLO
< V
IN
< V
OVLO,
time for GATE to go
low (Figure 1)
V
GATE
= 5V to 0.5V
(MAX4923/MAX4924/MAX4925) or
V
GATE
= 4V to 0.5V (MAX4926) (Figure 1)
V
IN
rising at 1V/µs from 5V to 8V
(MAX4923/MAX4924/MAX4925) or from 4V
to 7V (MAX4926) to V
GATE
= V
IN
-0.5V
(Figure 1)
V
IN
rising at 1V µs from 5V to 8V
(MAX4923/MAX4924/MAX4925) or from 4V
to 7V (MAX4926), to V
FLAG
= 2.4V,
R
FLAG
= 10kΩ to 3V (Figure 1)
10
20
34
ms
I
IN
V
OH
I
PD
V
OL
I
LKG
MAX4923/MAX4924/MAX4925
MAX4926
V
IN
> 8V, I
SOURCE
= 0.1mA
V
GATE
= V
IN
I
SINK
= 1mA
V
FLAG
= 5.5V
-1
V
IN
-
0.2
6.5
12
0.4
+1
UVLO
V
IN
falling
2.378
CONDITIONS
MIN
1.8
7.00
6.00
5.50
4.35
7.18
6.16
5.65
4.46
65
55
50
40
2.439
20
14
13
25
23
2.500
V
mV
µA
V
mA
V
µA
mV
TYP
MAX
28.0
7.36
6.31
5.79
4.57
V
UNITS
V
Gate Turn-on Time
t
GON
0.6
µs
Gate Turn-Off Time
t
GOFF
5
20
µs
Flag Assertion Delay
t
FLAG
4.5
µs
Note 1:
All devices are 100% tested at +25°C. Electrical limits across the full temperature range are guaranteed by design and characterization.
2
_______________________________________________________________________________________
Overvoltage Protectors with
External pFET
Typical Operating Characteristics
(V
IN
= +5V for MAX4923/MAX4924/MAX4925, V
IN
= +4V for MAX4926 (pFET = Si6991DQ), T
A
= +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. INPUT VOLTAGE
MAX4923 toc01
MAX4923–MAX4926
GATE VOLTAGE vs. INPUT VOLTAGE
MAX4925
8
GATE VOLTAGE (V)
MAX4923 toc02
GATE-OUTPUT LOW VOLTAGE
vs. GATE SINK CURRENT
MAX4923 toc03
100
10
250
GATE OUTPUT LOW VOLTAGE (mV)
80
SUPPLY CURRENT (μA)
MAX4925
60
200
V
CC
= +2.5V
150
V
CC
= +3.3V
6
40
MAX4926
4
100
20
2
50
V
CC
= +5.5V
0
0
4
8
12
16
20
24
28
INPUT VOLTAGE (V)
0
2
4
6
8
INPUT VOLTAGE (V)
0
0
200
400
600
800
GATE SINK CURRENT (μA)
1000
SUPPLY CURRENT vs. TEMPERATURE
MAX4926
V
CC
= +4V
14
SUPPLY CURRENT (μA)
MAX4923 toc04
POWER-UP RESPONSE
MAX4923 toc05
POWER-UP RESPONSE
MAX4923 toc06
15
V
IN
5V/div
5V/div
V
IN
5V/div
V
OUT
13
5V/div
12
5V/div
VFLAG
10
-40
-15
10
35
60
85
20.0 ms
10.0ms
TEMPERATURE (°C)
V
GATE
1A/div
I
IN
5V/div
V
FLAG
11
OVERVOLTAGE RESPONSE
MAX4923 toc07
POWER-UP OVERVOLTAGE RESPONSE
MAX4923 toc08
5V/div
V
IN
5V/div
V
IN
5V/div
V
GATE
5V/div
V
GATE
10mA/div
I
GATE
5V/div
V
FLAG
5V/div
V
FLAG
20.0μs
10.0ms
_______________________________________________________________________________________
3
Overvoltage Protectors with
External pFET
MAX4923–MAX4926
Pin Description
PIN
1
2
3
4
5, 6
NAME
IN
GND
FLAG
GATE
N.C.
FUNCTION
Voltage Input. IN is both the power-supply input and the overvoltage/undervoltage sense input. Bypass IN to
GND with a 1µF ceramic capacitor as close as possible to the device to enable ±15kV (HBM) ESD protection
on IN.
Ground
Fault Indication Open-Drain Output. FLAG deasserts high during undervoltage and overvoltage lockout
conditions. FLAG asserts low during normal operation.
pFET Gate Drive Output. GATE is driven high during a fault condition to turn off the external pFET. When
V
UVLO
< V
IN
< V
OVLO,
GATE is driven low and the external pFET is turned on.
No Connection. Not internally connected. Leave N.C. unconnected.
Functional Diagram
IN
GATE DRIVER
GATE
MAX4923–MAX4926
GND
OVLO AND
UVLO
DETECTOR
CONTROL
LOGIC AND
TIMER
FLAG
V
OVLO
V
IN
t
DEB
t
GOFF
V
IN
- 0.5V
t
DEB
t
GOFF
V
UVLO
V
IN
- 0.5V
V
GATE
O.5V
t
GON
t
FLAG
t
GON
O.5V
t
FLAG
3V
V
FLAG
Figure 1. Timing Diagram
4
_______________________________________________________________________________________
Overvoltage Protectors with
External pFET
MAX4923–MAX4926
STANDBY
GATE = HIGH
FLAG = HIGH
V
UVLO
< V
IN
< V
OVLO
INPUT
SYSTEM
LOADS
ADAPTER WITH
BUILT-IN
BATTERY
CHARGER
P
OUTPUT
+
LITHIUM ION
BATTERY
-
1
IN
GATE
4
V
IN
< V
UVLO
TIME STARTS
COUNTING
t = 20ms
V
IN
> V
OVLO
MAX4926
V
I0
2
GND
FLAG
3
ON
GATE = LOW
FLAG = LOW
Figure 2. State Machine
Figure 3. MAX4926 Typical Operating Circuit
Detailed Description
The MAX4923–MAX4926 overvoltage protection
controllers protect low-voltage systems against high-
voltage faults of up to +28V when used with a -30V
pFET. When the input voltage exceeds the OVLO
threshold, these devices turn off the external pFET to
prevent damage to protected components.
The typical overvoltage trip level is set to 7.18V
(MAX4923), 6.16V (MAX4924), 5.65V (MAX4925), and
4.46V (MAX4926). When the supply drops below the
UVLO threshold, the devices turn off the external pFET.
IN is ESD protected to +15kV (Human Body Model) when
bypassed with a 1µF ceramic capacitor to ground.
Device Operation
The MAX4923–MAX4926 have an on-board state
machine to control device operation. A flowchart is
shown in Figure 2. At initial power up, if V
IN
< V
UVLO
or
if V
IN
> V
OVLO
, both GATE and FLAG are high. When
V
UVLO
< V
IN
< V
OVLO
, an internal timer starts counting
and the device enters its on state after a 20ms delay. At
any time if V
IN
drops below V
UVLO
or above V
OVLO
,
both GATE and FLAG transition high.
Application Information
MAX4926 Application
In a typical application for the MAX4926, an external
adapter with built-in battery charger is connected to IN
and a battery is connected to the drain of the external
FET. When the adapter is unplugged, IN is directly con-
nected to the battery through the external FET. Since
the battery voltage is typically greater than V
UVLO
, the
GATE voltage stays low and the device remains pow-
ered by the battery.
Undervoltage Lockout (UVLO)
The MAX4923–MAX4926 have a fixed 2.44V (typ)
UVLO level. When V
IN
is less than V
UVLO
, GATE is high
and FLAG is high.
Overvoltage Lockout (OVLO)
The MAX4923 has a 7.18V (typ) OVLO; the MAX4924
has a 6.16V (typ) OVLO; the MAX4925 has a 5.65V
(typ) OVLO; and the MAX4926 has a 4.46V (typ) OVLO.
When V
IN
is greater than V
OVLO
, GATE is high and
FLAG is high.
MOSFET Selection
The MAX4923–MAX4926 are designed for use with
either a single pFET or dual pFETs in parallel.
MOSFETs with R
DS(ON)
specified for a V
GS
of -4.5V are
recommended. For input supplies near the UVLO maxi-
mum of 2.5V, use a MOSFET specified for a lower V
GS
voltage. Also, the V
DS
must be -30V and the V
GS
(max)
must be higher than the V
OVLO
(max) for the MOSFET
to withstand the full +28V input range of the
MAX4923–MAX4926.
FLAG Output
The open-drain FLAG output is used to signal to the
host system that there is a fault with the input voltage.
FLAG goes high during an overvoltage or undervoltage
fault. Connect a pullup resistor from FLAG to the logic
I/O voltage of the host system.
_______________________________________________________________________________________
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