1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = HIGH Impedance.
= LOW-to-HIGH Transition.
2. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature
range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
CC
or ground.
4. Typical values are at V
CC
= 5.0V, T
A
= +25°C ambient.
5. This parameter is guaranteed but not tested.
6. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I
OS
tests should be performed last.
7. Tested at +25°C.
2
CY74FCT16374T
CY74FCT162374T
Output Drive Characteristics for CY74FCT162374T
Parameter
I
ODL
I
ODH
V
OH
V
OL
Description
Output LOW Current
[6]
Output HIGH Current
[6]
Output HIGH Voltage
Output LOW Voltage
Test Conditions
V
CC
=5V, V
IN
=V
IH
or V
IL
, V
OUT
=1.5V
V
CC
=5V, V
IN
=V
IH
or V
IL
, V
OUT
=1.5V
V
CC
=Min., I
OH
=−24 mA
V
CC
=Min., I
OL
=24 mA
Min.
60
−60
2.4
Typ.
[4]
115
−115
3.3
0.3
0.55
Max.
150
−150
Unit
mA
mA
V
V
Capacitance
[5]
(T
A
= +25°C, f = 1.0 MHz)
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
V
IN
= 0V
V
OUT
= 0V
Test Conditions
Typ.
[4]
4.5
5.5
Max.
6.0
8.0
Unit
pF
pF
Power Supply Characteristics
Parameter
I
CC
∆I
CC
I
CCD
Description
Quiescent Power Supply Current V
CC
=Max.
Quiescent Power Supply Current
(TTL inputs HIGH)
Dynamic Power Supply
Current
[9]
Total Power Supply Current
[10]
V
CC
=Max.
V
CC
=Max., One Input
Toggling, 50% Duty Cycle,
Outputs Open, OE=GND
V
CC
=Max., f
0
=10 MHz,
f
1
=5 MHz, 50% Duty Cycle,
Outputs Open, One Bit
Toggling, OE=GND
V
CC
=Max., f
0
=10 MHz,
f
1
=2.5 MHz, 50% Duty
Cycle, Outputs Open, Sixteen
Bits Toggling, OE=GND
Test Conditions
V
IN
≤0.2V,
V
IN
≥V
CC
−0.2V
V
IN
=3.4V
[8]
V
IN
=V
CC
or
V
IN
=GND
V
IN
=V
CC
or
V
IN
=GND
V
IN
=3.4V or
V
IN
=GND
V
IN
=V
CC
or
V
IN
=GND
V
IN
=3.4V or
V
IN
=GND
Typ.
[4]
5
0.5
60
Max.
500
1.5
100
Unit
µA
mA
µA/
MHz
mA
mA
mA
mA
I
C
0.6
1.1
3.0
7.5
1.5
3.0
5.5
[11]
19.0
[11]
Note:
8. Per TTL driven input (V
IN
=3.4V); all other inputs at V
CC
or GND.
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
10. I
C
I
C
= I
CC
+∆I
CC
D
H
N
T
+I
CCD
(f
0
/2 + f
1
N
1
)
I
CC
= Quiescent Current with CMOS input levels
∆I
CC
= Power Supply Current for a TTL HIGH input (V
IN
=3.4V)
= Duty Cycle for TTL inputs HIGH
D
H
N
T
= Number of TTL inputs at D
H
I
CCD
= Dynamic Current caused by an input transition pair (HLH or LHL)
f
0
= Clock frequency for registered devices, otherwise zero
= Input signal frequency
f
1
N
1
= Number of inputs changing at f
1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
3
CY74FCT16374T
CY74FCT162374T
Switching Characteristics
Over the Operating Range
[12]
CY74FCT16374T
CY74FCT162374T
Parameter
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
t
SK(O)
Description
Propagation Delay
CLK to O
Output Enable Time
Output Disable Time
Set-Up Time HIGH or LOW,
D to CLK
Hold Time HIGH or LOW,
D to CLK
CLK Pulse Width
HIGH or LOW
Output Skew
[14]
Min.
2.0
1.5
1.5
2.0
1.5
5.0
0.5
CY74FCT16374CT
CY74FCT162374CT
Parameter
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
t
SK(O)
Description
Propagation Delay
CLK to O
Output Enable Time
Output Disable Time
Set-Up Time HIGH or LOW,
D to CLK
Hold Time HIGH or LOW,
D to CLK
CLK Pulse Width
HIGH or LOW
Output Skew
[14]
Min.
2.0
1.5
1.5
2.0
1.5
3.3
0.5
Max.
5.2
5.5
5.0
Max.
10.0
12.5
8.0
CY74FCT16374AT
CY74FCT162374AT
Min.
2.0
1.5
1.5
2.0
1.5
5.0
0.5
CY74FCT16374ET
CY74FCT162374ET
Min.
2.0
1.5
1.5
1.5
0.0
3.0
0.5
Max.
3.7
4.4
3.6
Unit
ns
ns
ns
ns
ns
ns
ns
Max.
6.5
6.5
5.5
Unit
ns
ns
ns
ns
ns
ns
ns
Fig.
No.
[13]
1, 5
1, 7, 8
1, 7, 8
4
4
5
Fig.
No.
[13]
1, 5
1, 7, 8
1, 7, 8
4
4
5
Notes:
12. Minimum limits are guaranteed but not tested on Propagation Delays.
13. See “Parameter Measurement Information” in the General Information section.
14. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
