D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Features
◆
◆
IDT71V016SA
◆
◆
◆
◆
◆
◆
64K x 16 advanced high-speed CMOS Static RAM
Equal access and cycle times
— Commercial: 10/12/15/20ns
— Industrial: 12/15/20ns
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
LVTTL-compatible
Low power consumption via chip deselect
Upper and Lower Byte Enable Pins
Single 3.3V power supply
Available in 44-pin Plastic SOJ, 44-pin TSOP, and
48-Ball Plastic FBGA packages
Description
The IDT71V016 is a 1,048,576-bit high-speed Static RAM organized
as 64K x 16. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs.
The IDT71V016 has an output enable pin which operates as fast
as 5ns, with address access times as fast as 10ns. All bidirectional
inputs and outputs of the IDT71V016 are LVTTL-compatible and operation
is from a single 3.3V supply. Fully static asynchronous circuitry is used,
requiring no clocks or refresh for operation.
The IDT71V016 is packaged in a JEDEC standard 44-pin Plastic
SOJ, a 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA.
Functional Block Diagram
Output
Enable
Buffer
OE
A
0
– A
15
Address
Buffers
Row / Column
Decoders
I/O
15
Chip
Enable
Buffer
Sense
Amps
and
Write
Drivers
8
Low
Byte
I/O
Buffer
8
8
High
Byte
I/O
Buffer
8
CS
I/O
8
WE
Write
Enable
Buffer
64K x 16
Memory
Array
16
I/O
7
I/O
0
BHE
Byte
Enable
Buffers
BLE
3834 drw 01
OCTOBER 2011
1
©2011 Integrated Device Technology, Inc.
DSC-3834/11
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Pin Configurations
A
4
A
3
A
2
A
1
A
0
CS
I/O
0
I/O
1
I/O
2
I/O
3
V
DD
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
15
A
14
A
13
A
12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SO44-1
SO44-2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
DD
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
8
A
9
A
10
A
11
NC
1
A
B
C
D
E
F
G
H
BLE
I/O
8
I/O
9
V
SS
V
DD
I/O
14
I/O
15
NC
2
OE
BHE
I/O
10
I/O
11
I/O
12
I/O
13
NC
A
8
3
A
0
A
3
A
5
NC
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
NC
A
15
A
13
A
10
5
A
2
CS
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
NC
I/O
0
I/O
2
V
DD
V
SS
I/O
6
I/O
7
NC
3834 tbl 02a
FBGA (BF48-1)
Top View
Pin Description
A
0
– A
15
CS
WE
OE
BHE
BLE
I/O
0
– I/O
15
V
DD
V
SS
Address Inputs
Chip Select
Write Enable
Output Enable
High Byte Enable
Low Byte Enable
Data Input/Output
3.3V Power
Ground
3834 drw 02
Input
Input
Input
Input
Input
Input
I/O
Power
Gnd
3834 tbl 01
SOJ/TSOP
Top View
Truth Table
(1)
CS
H
L
L
L
L
L
L
L
L
OE
X
L
L
L
X
X
X
H
X
WE
X
H
H
H
L
L
L
H
X
BLE
X
L
H
L
L
L
H
X
H
BHE
X
H
L
L
L
H
L
X
H
I/O
0
-I/O
7
High-Z
DATA
OUT
High-Z
DATA
OUT
DATA
IN
DATA
IN
High-Z
High-Z
High-Z
I/O
8
-I/O
15
High-Z
High-Z
DATA
OUT
DATA
OUT
DATA
IN
High-Z
DATA
IN
High-Z
High-Z
Function
Deselected – Standby
Low Byte Read
High Byte Read
Word Read
Word Write
Low Byte Write
High Byte Write
Outputs Disabled
Outputs Disabled
NOTE:
1. H = V
IH
, L = V
IL
, X = Don't care.
3834 tbl 02
6.42
2
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
DD
V
IN
, V
OUT
T
BIAS
T
STG
P
T
I
OUT
Rating
Supply Voltage Relative to
V
SS
Terminal Voltage Relative
to V
SS
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–0.5 to +4.6
–0.5 to V
DD
+0.5
–55 to +125
–55 to +125
1.25
50
Unit
V
V
o
o
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Temperature
0°C to +70°C
-40°C to +85°C
V
SS
0V
0V
V
DD
See Below
See Below
3834 tbl 04
C
C
W
mA
Recommended DC Operating
Conditions
Symbol
V
DD
(1)
V
DD
(2)
Vss
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.15
3.0
0
2.0
–0.3
(4)
Typ.
3.3
3.3
0
____
____
Max.
3.6
3.6
0
V
DD
+0.3
(3)
0.8
Unit
V
V
V
V
V
3834 tbl 05
3834 tbl 03
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Capacitance
Symbol
C
IN
C
I/O
(T
A
= +25°C, f = 1.0MHz, SOJ package)
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
6
7
Unit
pF
pF
NOTES:
1. For 71V016SA10 only.
2. For all speed grades except 71V016SA10.
3. V
IH
(max.) = V
DD
+2V for pulse width less than 5ns, once per cycle.
4. V
IL
(min.) = –2V for pulse width less than 5ns, once per cycle.
3834 tbl 06
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
DC Electrical Characteristics
(V
DD
= Min. to Max., Commercial and Industrial Temperature Ranges)
IDT71V016SA
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Condition
V
DD
= Max., V
IN
= V
SS
to V
DD
V
DD
= Max.,
CS
= V
IH
, V
OUT
= V
SS
to V
DD
I
OL
= 8mA, V
DD
= Min.
I
OH
= –4mA, V
DD
= Min.
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
3834 tbl 07
2.4
DC Electrical Characteristics
(1,2)
(V
DD
= Min. to Max., V
LC
= 0.2V, V
HC
= V
DD
– 0.2V)
Symbol
I
CC
Parameter
Dynamic Operating Current
CS
≤
V
LC
, Outputs Open, V
DD
= Max., f = f
MAX
(3)
Dynamic Standby Power Supply Current
CS
≥
V
HC
, Outputs Open, V
DD
= Max., f = f
MAX
(3)
Full Standby Power Supply Current (static)
CS
≥
V
HC
, Outputs Open, V
DD
= Max., f = 0
(3)
Max.
Typ.
(4)
(5)
71V016SA10
Com'l Only
160
65
45
10
71V016SA12
Com'l
150
60
40
10
Ind
160
--
45
10
71V016SA15
Com'l
130
55
35
10
Ind
130
--
35
10
71V016SA20
Com'l
120
50
30
10
Ind
120
--
30
10
mA
mA
3834 tbl 08
Unit
mA
I
SB
I
SB1
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and V
DD
– 0.2V (High).
3. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing .
4. Typical values are based on characterization data for H step only measured at 3.3V, 25°C and with equal read and write cycles.
6.42
3
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
1.5ns
1.5V
1.5V
See Figure 1, 2 and 3
3834 tbl 09
AC Test Loads
3.3V
+1.5V
50Ω
I/O
Z
0
= 50Ω
30pF
3834 drw 03
320Ω
DATA
OUT
5pF*
350Ω
3834 drw 04
*Including jig and scope capacitance.
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
7
Δt
AA,
t
ACS
(Typical, ns) 5
4
3
•
•
•
6
2
1
•
•
•
•
8 20 40
60 80 100 120 140 160 180 200
CAPACITANCE (pF)
3834 drw 05
Figure 3. Output Capacitive Derating
6.42
4
单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
