Low Skew, 1-to-12 LVCMOS/ LVTTL
Clock Multiplier/ Zero Delay Buffer
87973I-147
Data Sheet
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
General Description
The 87973I-147 is a LVCMOS/LVTTL clock generator. The
87973I-147 has three selectable inputs and provides 14
LVCMOS/LVTTL outputs.
The 87973I-147 is a highly flexible device. The three selectable
inputs (1 differential and 2 single ended inputs) are often used in
systems requiring redundant clock sources. Up to three different
output frequencies can be generated among the three output banks.
The three output banks and feedback output each have their own
output dividers which allows the device to generate a multitude of
different bank frequency ratios and output-to-input frequency ratios.
In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be
inverting or non-inverting. The output frequency range is 10MHz to
150MHz. The input frequency range is 6MHz to 120MHz.
The 87973I-147 also has a QSYNC output which can be used for
system synchronization purposes. It monitors Bank A and Bank C
outputs and goes low one period prior to coincident rising edges of
Bank A and Bank C clocks. QSYNC then goes high again when the
coincident rising edges of Bank A and Bank C occur. This feature is
used primarily in applications where Bank A and Bank C are running
at different frequencies, and is particularly useful when they are
running at non-integer multiples of one another.
Features
•
Fully integrated PLL
•
Fourteen LVCMOS/LVTTL outputs to include: twelve clocks,
one feedback, one sync
•
Selectable differential CLK, nCLK inputs or LVCMOS/LVTTL
reference clock inputs
•
CLK0, CLK1 can accept the following input levels:
LVCMOS or LVTTL
•
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Output frequency range: 10MHz to 150MHz
•
VCO range: 240MHz to 500MHz
•
Output skew: 200ps (maximum)
•
Cycle-to-cycle jitter, (all banks
÷4):
55ps (maximum)
•
Full 3.3V supply voltage
•
-40°C to 85°C ambient operating temperature
•
Compatible with PowerPC™and Pentium™Microprocessors
•
Available in lead-free packages
•
For drop-in replacement use 87973i
Example Applications:
1.System
Clock generator:
Use a 16.66MHz reference clock to
generate eight 33.33MHz copies for PCI and four 100MHz copies
for the CPU or PCI-X.
2.Line
Card Multiplier:
Multiply differential 62.5MHz from a back
plane to single-ended 125MHz for the line Card ASICs and Gigabit
Ethernet Serdes.
3.Zero
Delay buffer for Synchronous memory:
Fanout up to twelve
100MHz copies from a memory controller reference clock to the
memory chips on a memory module with zero delay.
Pin Assignment
GNDO
QB0
V
DDO
QB1
GNDO
QB2
V
DDO
QB3
EXT_FB
GNDO
QFB
V
DD
FSEL_FB0
39 38 37 36 35 34 33 32 31 30 29 28 27
FSEL_B1
FSEL_B0
FSEL_A1
FSEL_A0
QA3
V
DDO
QA2
GNDO
QA1
V
DDO
QA0
GNDO
VCO_SEL
40
41
42
43
44
45
46
47
48
49
50
51
52
1
GNDI
26
25
24
23
22
21
20
19
18
17
16
15
14
87973I-147
FSEL_FB1
QSYNC
GNDO
QC0
V
DDO
QC1
FSEL_C0
FSEL_C1
QC2
V
DDO
QC3
GNDO
INV_CLK
2 3 4 5 6 7 8 9 10 11 12 13
FRZ_DATA
FSEL_FB2
PLL_SEL
REF_SEL
CLK_SEL
CLK0
CLK1
CLK
nCLK
nMR/OE
FRZ_CLK
V
DDA
52-Lead, 10mm x 10mm LQFP
©2016 Integrated Device Technology, Inc
1
June 28, 2016
87973I-147 Data Sheet
Pin Descriptions and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1
2
3
4
5,
26,
27
6
Name
GNDI
nMR/OE
FRZ_CLK
FRZ_DATA
FSEL_FB2,
FSEL_FB1,
FSEL_FB0
PLL_SEL
Type
Power
Input
Input
Input
Input
Pullup
Pullup
Pullup
Pullup
Description
Power supply ground.
Master reset and output enable. When HIGH, enables the outputs.
When LOW, resets the outputs in a high-impedance state and resets output divide
circuitry. Enables and disables all outputs. LVCMOS / LVTTL interface levels.
Clock input for freeze circuitry. LVCMOS / LVTTL interface levels.
Configuration data input for freeze circuitry. LVCMOS / LVTTL interface levels.
Select pins control Feedback Divide value. LVCMOS / LVTTL interface levels.
See Table 3B.
Selects between the PLL and reference clocks as the input to the output dividers.
When HIGH, selects PLL. When LOW, bypasses the PLL and reference clocks.
LVCMOS / LVTTL interface levels.
Selects between CLK0 or CLK1 and CLK, nCLK inputs. When LOW, selects CLK0
or CLK1. When HIGH, CLK, nCLK inputs. LVCMOS / LVTTL interface levels.
Clock select input. When LOW, selects CLK0. When HIGH, selects CLK1.
LVCMOS / LVTTL interface levels.
Single-ended reference clock inputs. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Input
Pullup
7
8
9, 10
11
12
13
14
15, 24, 30, 35,
39, 47, 51
16, 18,
21, 23
17, 22, 33, 37,
45, 49
19,
20
25
28
29
31
32, 34,
36, 38
40,
41
42,
43
44, 46
48, 50
52
REF_SEL
CLK_SEL
CLK0, CLK1
CLK
nCLK
V
DDA
INV_CLK
GNDO
QC3, QC2,
QC1, QC0
V
DDO
FSEL_C1,
FSEL_C0
QYSNC
V
DD
QFB
EXT_FB
QB3, QB2,
QB1, QB0
FSEL_B1,
FSEL_B0
FSEL_A1,
FSEL_A0
QA3, QA2,
QA1, QA0
VCO_SEL
Input
Input
Input
Input
Input
Power
Input
Power
Output
Power
Input
Output
Power
Output
Input
Output
Input
Input
Output
Input
Pullup
Pullup
Pullup
Pullup
Pullup/
Inverting differential clock input. V
DD
/2 default when left floating.
Pulldown
Analog supply pin.
Pullup
Inverted clock select for QC2 and QC3 outputs. LVCMOS / LVTTL interface levels.
Power supply ground.
Single-ended Bank C clock outputs. LVCMOS/ LVTTL interface levels.
Output power supply pins.
Pullup
Select pins for Bank C outputs. LVCMOS / LVTTL interface levels. See Table 3A.
Synchronization output for Bank A and Bank C. Refer to Figure 1, Timing Diagrams.
LVCMOS / LVTTL interface levels.
Power supply pin.
Single-ended feedback clock output. LVCMOS / LVTTL interface levels.
Pullup
External feedback. LVCMOS / LVTTL interface levels.
Single-ended Bank B clock outputs. LVCMOS/ LVTTL interface levels.
Pullup
Pullup
Select pins for Bank B outputs. LVCMOS / LVTTL interface levels. See Table 3A.
Select pins for Bank A outputs. LVCMOS / LVTTL interface levels. See Table 3A.
Single-ended Bank A clock outputs. LVCMOS/ LVTTL interface levels.
Pullup
Selects VCO. When HIGH, selects VCO ÷ 1. When LOW, selects VCO ÷ 2.
LVCMOS / LVTTL interface levels.
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
©2016June 28, 2016 Integrated Device Tech-
4
June 28, 2016
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