LH543601
FEATURES
•
Fast Cycle Times: 20/25/30/35 ns
•
Pin-Compatible and Functionally-Compatible
0.7µ-Technology Replacement for Sharp LH5420
256
×
36
×
2 Bidirectional FIFO
FUNCTIONAL DESCRIPTION
The LH543601 contains two FIFO buffers, FIFO #1
and FIFO #2. These operate in parallel, but in opposite
directions, for bidirectional data buffering. FIFO #1 and
FIFO #2 each are organized as 256 by 36 bits. The
LH543601 is ideal either for wide unidirectional applica-
tions or for bidirectional data applications; component
count and board area are reduced.
The LH543601 has two 36-bit ports, Port A and Port B.
Each port has its own port-synchronous clock, but the two
ports may operate asynchronously relative to each other.
Data flow is initiated at a port by the rising edge of the
appropriate clock; it is gated by the corresponding edge-
sampled enable, request, and read/write control signals.
At the maximum operating frequency, the clock duty cycle
may vary from 40% to 60%. At lower frequencies, the
clock waveform may be quite asymmetric, as long as the
minimum pulse-width conditions for clock-HIGH and
clock-LOW remain satisfied; the LH543601 is a fully-static
part.
Conceptually, the port clocks CK
A
and CK
B
are free-
running, periodic ‘clock’ waveforms, used to control other
signals which are edge-sensitive. However, there actually
is not any absolute requirement that these ‘clock’ wave-
forms
must
be periodic. An ‘asynchronous’ mode of
operation is possible, in one or both directions, inde-
pendently, if the appropriate enable and request inputs
are continuously asserted, and enough aperiodic ‘clock’
pulses of suitable duration are generated by external logic
to cause all necessary actions to occur.
A synchronous request/acknowledge handshake
facility is provided at each port for FIFO data access. This
request/ acknowledge handshake resolves FIFO full and
empty boundary conditions, when the two ports are op-
erated asynchronously relative to each other.
FIFO status flags monitor the extent to which each
FIFO buffer has been filled. Full, Almost-Full, Half-Full,
Almost-Empty, and Empty flags are included for
each
FIFO. The Almost-Full and Almost-Empty flags are pro-
grammable over the entire FIFO depth, but are automat-
ically initialized to eight locations from the respective FIFO
boundaries at reset. A data block of 256 or fewer words
may be retransmitted any desired number of times.
•
•
•
•
Two 256
×
36-bit FIFO Buffers
Full 36-bit Word Width
Selectable 36/18/9-bit Word Width on Port B
Independently-Synchronized (‘Fully-Asynchronous’)
Operation of Port A and Port B
Both Ports
•
‘Synchronous’ Enable-Plus-Clock Control at
•
R/W, Enable, Request, and Address Control Inputs
are Sampled on the Rising Clock Edge
•
Synchronous Request/Acknowledge ‘Handshake’
Capability; Use is Optional
•
Device Comes Up Into a Known Default State at
Reset; Programming is Allowed, but is not Required
•
Asynchronous Output Enables
•
Five Status Flags per Port: Full, Almost-Full,
Half-Full, Almost-Empty, and Empty
•
Almost-Full Flag and Almost-Empty Flag are
Programmable
•
•
•
•
•
Mailbox Registers with Synchronized Flags
Data-Bypass Function
Data-Retransmit Function
Automatic Byte Parity Checking
8 mA-I
OL
High-Drive Three-State Outputs with
Built-In Series Resistor
•
TTL/CMOS-Compatible I/O
•
Space-Saving PQFP and TQFP Packages
•
PQFP to PGA Package Conversion
1
NOTE:
1. For PQFP-to-PGA conversion for thru-hole board designs, Sharp
recommends ITT Pomona Electronics’ SMT/PGA Generic
Converter model #5853.
®
This converter maps the LH543601
132-pin PQFP to a generic 13
×
13, 132-pin PGA (100-mil
pitch). For more information, contact Sharp or ITT Pomona
Electronics at 1500 East Ninth Street, Pomona, CA 91766,
(909) 469-2900.
1
LH543601
256
×
36
×
2 Bidirectional FIFO
tion or configuration information directly, to or from a
peripheral device on Port B, during system startup.
A word-width-select option is provided on Port B for
36-bit, 18-bit, or 9-bit data access. This feature allows
word-width matching between Port A and Port B, with no
additional logic needed. It also ensures maximum utiliza-
tion of bus bandwidths.
A Byte Parity Check Flag at each port monitors data
integrity. Control-Register bit 0 (zero) selects the parity
mode, odd or even. This bit is initialized for odd data parity
at reset; but it may be reprogrammed for even parity, or
back again to odd parity, as desired.
FUNCTIONAL DESCRIPTION (cont’d)
Two mailbox registers provide a separate path for
passing control words or status words between ports.
Each mailbox has a New-Mail-Alert Flag, which is syn-
chronized to the reading port’s clock. This mailbox func-
tion facilitates the synchronization of data transfers
between asynchronous systems.
Data-bypass mode allows Port A to directly transfer
data to or from Port B at reset. In this mode, the device
acts as a registered transceiver under the control of
Port A. For instance, a master processor on Port A can
use the data bypass feature to send or receive initializa-
PIN CONNECTIONS
D
11A
D
12A
D
13A
D
14A
V
SSO
D
15A
D
16A
D
17A
PF
A
HF
1
AF
1
FF
1
V
CC
OE
A
A
2A
A
1A
A
0A
CK
A
R/W
A
EN
A
REQ
A
V
SS
ACK
A
EF
2
AE
2
MBF
2
D
18A
D
19A
V
SSO
D
20A
D
21A
D
22A
D
23A
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Pin 1
Pin 132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
V
CCO
D
10A
D
9A
D
8A
V
SSO
D
7A
D
6A
D
5A
V
CCO
D
4A
D
3A
D
2A
V
SSO
D
1A
D
0A
RS
RT
1
D
0B
D
1B
D
2B
V
SSO
D
3B
D
4B
D
5B
V
CCO
D
6B
D
7B
D
8B
V
SSO
D
9B
D
10B
D
11B
V
CCO
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
CHAMFERED
EDGE
TOP VIEW
V
CCO
D
24A
D
25A
D
26A
V
SSO
D
27A
D
28A
D
29A
V
CCO
D
30A
D
31A
D
32A
V
SSO
D
33A
D
34A
D
35A
RT
2
V
SS
D
35B
D
34B
V
SSO
D
33B
D
32B
D
31B
V
CCO
D
30B
D
29B
D
28B
V
SSO
D
27B
D
26B
D
25B
V
CCO
D
12B
D
13B
D
14B
D
15B
V
SSO
D
16B
D
17B
MBF
1
AE
1
EF
1
ACK
B
V
SS
REQ
B
EN
B
R/W
B
CK
B
A
0B
WS
0
WS
1
OE
B
V
CC
FF
2
AF
2
HF
2
PF
B
D
18B
D
19B
D
20B
V
SSO
D
21B
D
22B
D
23B
D
24B
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
543601-30
Figure 1. Pin Connections for 132-Pin PQFP Package
(Top View)
2
嵌入式系统
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