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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4351
8-channel analog
multiplexer/demultiplexer with latch
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
8-channel analog
multiplexer/demultiplexer with latch
FEATURES
•
Wide analog input voltage range:
±
5V
•
Low “ON” resistance:
80
Ω
(typ.) at V
CC
−
V
EE
= 4.5 V
70
Ω
(typ.) at V
CC
−
V
EE
= 6.0 V
60
Ω
(typ.) at V
CC
−
V
EE
= 9.0 V
•
Logic level translation: to enable 5 V logic to
communicate with
±
5 V analog signals
•
Typical “break before make” built in
•
Address latches provided
•
Output capability: non-standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4351 are high-speed Si-gate CMOS
devices. They are specified in compliance with JEDEC
standard no. 7A.
74HC/HCT4351
The 74HC/HCT4351 are 8-channel analog
multiplexers/demultiplexers with three select inputs (S
0
to
S
2
), two enable inputs (E
1
and E
2
), a latch enable input
(LE), eight independent inputs/outputs (Y
0
to Y
7
) and a
common input/output (Z).
With E
1
LOW and E
2
is HIGH, one of the eight switches is
selected (low impedance ON-state) by S
0
to S
2
. The data
at the select inputs may be latched by using the active
LOW latch enable input (LE). When LE is HIGH the latch
is transparent. When either of the two enable inputs,
E
1
(active LOW) and E
2
(active HIGH), is inactive, all 8
analog switches are turned off.
V
CC
and GND are the supply voltage pins for the digital
control inputs (S
0
to S
2
, LE, E
1
and E
2
). The V
CC
to GND
ranges are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT.
The analog inputs/outputs (Y
0
to Y
7
, and Z) can swing
between V
CC
as a positive limit and V
EE
as a negative
limit.
V
CC
−
V
EE
may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, V
EE
is
connected to GND (typically ground).
QUICK REFERENCE DATA
V
EE
= GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PZH
/ t
PZL
t
PHZ
/ t
PLZ
C
I
C
PD
C
S
PARAMETER
turn “ON” time E
1
, E
2
or S
n
to V
os
turn “OFF” time E
1
, E
2
or S
n
to V
os
input capacitance
power dissipation capacitance per switch
max. switch capacitance
independent (Y)
common (Z)
Notes
1. C
PD
is used to determine the dynamic power
dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+∑ {(C
L
+ C
S)
×
V
CC2
×
f
o
}
where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
C
L
= output load capacitance in pF
C
S
= max. switch capacitance in pF
∑
{(C
L
+ C
S)
×
V
CC2
×
f
o
} = sum of outputs
V
CC
= supply voltage in V
December 1990
2
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package
Information”.
5
25
5
25
pF
pF
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; R
L
= 1 kΩ; V
CC
= 5 V
27
21
3.5
25
HCT
35
23
3.5
25
ns
ns
pF
pF
UNIT
Philips Semiconductors
Product specification
8-channel analog multiplexer/demultiplexer
with latch
PIN DESCRIPTION
PIN NO.
4
3, 14
7
8
9
10
11
15, 13, 12
17, 18, 19, 16, 1, 6, 2, 5
20
SYMBOL
Z
n.c.
E
1
E
2
V
EE
GND
LE
S
0
to S
2
Y
0
to Y
7
V
CC
NAME AND FUNCTION
common
not connected
enable input (active LOW)
enable input (active HIGH)
negative supply voltage
ground (0 V)
latch enable input (active LOW)
select inputs
independent inputs/outputs
positive supply voltage
74HC/HCT4351
Fig.1 Pin configuration.
Fig.2
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-channel analog multiplexer/demultiplexer
with latch
FUNCTION TABLE
INPUTS
E
1
H
X
L
L
L
L
L
L
L
L
L
X
Notes
1. Last selected channel “ON”.
2. Selected channels latched.
3. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↓
= HIGH-to-LOW LE transition
APPLICATIONS
•
Analog multiplexing and demultiplexing
•
Digital multiplexing and demultiplexing
•
Signal gating
X
L
H
H
H
H
H
H
H
H
H
X
E
2
LE
X
X
H
H
H
H
H
H
H
H
L
↓
S
2
X
X
L
L
L
L
H
H
H
H
X
X
S
1
X
X
L
L
H
H
L
L
H
H
X
X
S
0
X
X
L
H
L
H
L
H
L
H
X
X
CHANNEL
ON
none
none
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
(1)
(2)
74HC/HCT4351
Fig.4 Functional diagram.
Fig.5 Schematic diagram (one switch).
December 1990
4
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