EPLD
CY7C340 EPLD Family
Multiple Array Matrix High-Density EPLDs
Features
• Erasable, user-configurable CMOS EPLDs capable of
implementing high-density custom logic functions
• 0.8-micron double-metal CMOS EPROM technology
(CY7C34X)
• Advanced 0.65-micron CMOS technology to increase
performance (CY7C34XB)
• Multiple Array MatriX architecture optimized for speed,
density, and straightforward design implementation
— Programmable Interconnect Array (PIA) simplifies
routing
— Flexible macrocells increase utilization
— Programmable clock control
— Expander product terms implement complex logic
functions
CY7C342B. This allows the designer to replace 50 or more
TTL packages with just one MAX EPLD. The family comes in
a range of densities, shown below. By standardizing on a few
MAX building blocks, the designer can replace hundreds of
different 7400 series part numbers currently used in most dig-
ital systems.
The family is based on an architecture of flexible macrocells
grouped together into Logic Array Blocks (LABs). Within the
LAB is a group of additional product terms called expander
product terms. These expanders are used and shared by the
macrocells, allowing complex functions of up to 35 product
terms to be easily implemented in a single macrocell. A Pro-
grammable Interconnect Array (PIA) globally routes all signals
within devices containing more than one LAB. This architec-
ture is fabricated on the Cypress 0.8-micron, double-lay-
er-metal CMOS EPROM process, yielding devices with signif-
icantly higher integration, density and system clock speed than
the largest of previous generation EPLDs. The CY7C34XB de-
vices are 0.65-micron shrinks of the original 0.8-micron family.
The CY7C34XBs offer faster speed bins for each device in the
Cypress MAX family.
The density and performance of the CY7C340 family is ac-
cessed using Cypress’s
Warp™, Warp
Professional™, or
Warp
Enterprise™ design software.
Warp
provides
state-of-the-art synthesis, fitting, simulation and other devel-
opment tools at a very low cost.
Warp
Professional or
Warp
Enterprise are sophisticated CAE tool that include behavior-
al simulation, graphical waveform editing and more. Consult
the datasheets for
Warp, Warp
Professional and
Warp
Enter-
prise™ for more information about these development tools.
General Description
The Cypress Multiple Array Matrix (MAX®) family of EPLDs
provides a user-configurable, high-density solution to gener-
al-purpose logic integration requirements. With the combina-
tion of innovative architecture and state-of-the-art process, the
MAX EPLDs offer LSI density without sacrificing speed.
The MAX architecture makes it ideal for replacing large
amounts of TTL SSI and MSI logic. For example, a 74161
counter utilizes only 3% of the 128 macrocells available in the
CY7C342B. Similarly, a 74151 8-to-1 multiplexer consumes
less than 1% of the over 1,000 product terms in the
Max Family Members
Feature
Macrocells
MAX Flip-Flops
MAX Latches
[1]
MAX Inputs
[2]
MAX Outputs
Packages
CY7C344(B)
32
32
64
23
16
28H,J,W,P
CY7C343(B)
64
64
128
35
28
44H,J
CY7C342B
128
128
256
59
52
68H,J,R
CY7C346(B)
128
128
256
84
64
84H,J 100R,N
CY7C341B
192
192
384
71
64
84H,J,R
Key: P—Plastic DIP; H—Windowed Ceramic Leaded Chip Carrier; J—Plastic J-Lead Chip Carrier; R—Windowed Pin Grid Array;
W—Windowed Ceramic DIP; N—Plastic Quad Flat Pack
Notes:
1. When all expander product terms are used to implement latches.
2. With one output.
PAL is a registered trademark of Advanced Micro Devices.
MAX is a registered trademark of Altera Corporation.
F
LASH
370,
Warp, Warp
Professional, and
Warp
Enterprise are trademarks of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 19, 2000
CY7C340 EPLD Family
DEDICATED INPUTS
MULTIPLE
ARRAYS
(LABS)
LOGIC
BLOCK
ARRAY
(LAB)
DUAL
I/O
FEEDBACK
EXPANDER
PRODUCT
TERMS
MACROCELLS
PROGRAMMABLE
INTERCONNECT
ARRAY (PIA)
C340–1
Figure 1. Key MAX Features
2
CY7C340 EPLD Family
Functional Description
The Logic Array Block
The logic array block, shown in
Figure 2,
is the heart of the
MAX architecture. It consists of a macrocell array, expander
product term array, and an I/O block. The number of mac-
rocells, expanders, and I/O vary, depending upon the de-
vice used. Global feedback of all signals is provided within
a LAB, giving each functional block complete access to the
LAB resources. The LAB itself is fed by the programmable
interconnect array and dedicated input bus. The feedbacks
of the macrocells and I/O pins feed the PIA, providing ac-
cess to them through other LABs in the device. The mem-
bers of the CY7C340 family of EPLDs that have a single
LAB use a global bus, so a PIA is not needed (see
Figure 3).
The MAX Macrocell
Traditionally, PLDs have been divided into either PLA (pro-
grammable AND, programmable OR), or PAL® (programma-
ble AND, fixed OR) architectures. PLDs of the latter type
provide faster input-to-output delays, but can be inefficient
due to fixed allocation of product terms. Statistical analysis
of PLD logic designs has shown that 70% of all logic func-
tions (per macrocell) require three product terms or less.
The macrocell structure of MAX has been optimized to handle
variable product term requirements. As shown in
Figure 4,
each macrocell consists of a product term array and a con-
figurable register. In the macrocell, combinatorial logic is
implemented with three product terms ORed together,
which then feeds an XOR gate. The second input to the
XOR gate is also controlled by a product term, providing
the ability to control active HIGH or active LOW logic and
to implement T- and JK-type flip-flops.
If more product terms are required to implement a given func-
tion, they may be added to the macrocell from the expander
product term array. These additional product terms may be
added to any macrocell, allowing the designer to build gate-in-
tensive logic, such as address decoders, adders, comparators,
and complex state machines, without using extra macrocells.
The register within the macrocell may be programmed for ei-
ther D, T, JK, or RS operation. It may alternately be configured
as a flow-through latch for minimum input-to-output delays, or
bypassed entirely for purely combinatorial logic. In addition,
each register supports both asynchronous preset and clear,
allowing asynchronous loading of counters of shift registers,
as found in many standard TTL functions. These registers may
be clocked with a synchronous system clock, or clocked inde-
pendently from the logic array.
Expander Product Terms
The expander product terms, as shown in
Figure 5,
are fed by
the dedicated input bus, the programmable interconnect ar-
ray, the macrocell feedback, the expanders themselves,
and the I/O pin feedbacks. The outputs of the expanders
then go to each and every product term in the macrocell
array. This allows expanders to be “shared” by the product
terms in the logic array block. One expander may feed all
macrocells in the LAB, or even multiple product terms in the
same macrocell. Since these expanders feed the second-
ary product terms (preset, clear, clock, and output enable)
of each macrocell, complex logic functions may be imple-
mented without utilizing another macrocell. Likewise, ex-
panders may feed and be shared by other expanders, to
implement complex multilevel logic and input latches.
MACROCELL
ARRAY
I/O
BLOCK
I/O
PINS
MACROCELL
ARRAY
I/O
BLOCK
I/O
PINS
I
N
P
U
T
S
P
I
A
I
N
P
U
T
S
EXPANDER
PRODUCT
TERM
ARRAY
EXPANDER
PRODUCT
TERM
ARRAY
PROGRAMMABLE
INTERCONNECT
ARRAY
C340–2
C340–3
Figure 2. Typical LAB Block Diagram
Figure 3. 7C344 LAB Block Diagram
3
CY7C340 EPLD Family
16
MACROCELL
FEEDBACKS
(32 FOR 7C344)
PROGRAMMABLE
INTERCONNECT
SIGNALS
D
PROGRAMMABLEFLIP–FLOP
(D, T,JK,SR)
D
REGISTEREDORFLOW–
I/O OUTPUT
ENABLE
D
THROUGH–LA TCH OPERATION
PROGRAMMABLECLOCK
D
ASYNCCLEARANDPRESET
PRESET
P
TO
I/O CONTROL
Q
C
ARRAY
CLOCK
CLEAR
MACROCELL
FEEDBACK
NOTE: ONE SYSTEM CL
OCK PER LAB
8
DEDICATED
INPUTS
32
EXPANDER
PRODUCT
TERMS
(64 FOR 7C344)
TO
PIA
C340–4
Figure 4. Macrocell Block Diagram
MACROCELL
P-TERMS
I/O OUTPUT
ENABLE
FROM
MACROCELL
IN LAB
I/O
PAD
THREE–STATE
BUFFER
TO PIA (LAB FOR 7C344)
EXPANDER
P-TERMS
C340–5
C340–6
Figure 5. Expander Product Terms
Figure 6. I/O Block Diagram
4
CY7C340 EPLD Family
I/O Block
Separate from the macrocell array is the I/O control block of
the LAB.
Figure 6
shows the I/O block diagram. The
three-state buffer is controlled by a macrocell product term
and the drives the I/O pad. The input of this buffer comes
from a macrocell within the associated LAB. The feedback
path from the I/O pin may feed other blocks within the LAB, as
well as the PIA. By decoupling the I/O pins from the flip-flops,
all the registers in the LAB are “buried,” allowing the I/O pins
to be used as dedicated outputs, bidirectional outputs, or as
additional dedicated inputs. Therefore, applications requiring
many buried flip-flops, such as counters, shift registers, and
state machines, no longer consume both the macrocell regis-
ter and the associated I/O pin, as in earlier devices.
The Programmable Interconnect Array
PLD density and speed has traditionally been limited by signal
routing; i.e., getting signals from one macrocell to another. For
smaller devices, a single array is used and all signals are avail-
able to all macrocells. But as the devices increase in density,
the number of signals being routed becomes very large, in-
creasing the amount of silicon used for interconnections. Also,
because the signal must be global, the added loading on the
internal connection path reduces
the overall speed performance of the device. The MAX archi-
tecture solves these problems. It is based on the concept of
small, flexible logic array blocks that, in the larger devices, are
interconnected by a PIA.
The PIA solves interconnect limitations by routing only the sig-
nals needed by each LAB. The architecture is designed so that
every signal on the chip is within the PIA. The PIA is then
programmed to give each LAB access to the signals that it
requires. Consequently, each LAB receives only the signals
needed. This effectively solves any routing problems that may
arise in a design without degrading the performance of the
device. Unlike masked or programmable gate arrays, which
induce variable delays dependent on routing, the PIA has a
fixed delay from point to point. This eliminates undesired
skews among logic signals, which may cause glitches in inter-
nal or external logic.
Warp
Enterprise
Warp
Enterprise provides even more features. It provides un-
limited timing simulation and source-level behavioral simula-
tion as well as a debugger. It has the ability to generate graph-
ical HDL blocks from HDL text. It can even generate
testbenches.
Warp
is available for PC and UNIX platforms. Some features
are not available in the UNIX version. For further information
see the
Warp
for PC,
Warp
for UNIX,
Warp
Professional and
Warp
Enterprise datasheets.
Third-Party Software
Although
Warp
is a complete CPLD development tool on its
own, it interfaces with nearly every third party EDA tool. All
major third-party software vendors provide support for the
MAX family of devices. To expedite this support, Cypress sup-
plies vendors with all pertinent architectural information as well
as design fitters for our products.
Programming
The
Impulse3™
device programmers from Cypress will pro-
gram all Cypress PLDs, CPLDs, FPGAs, and PROMs. The
unit is a standalone programmer that connects to any
IBM-compatible PC via the printer port.
Third-Party Programmers
As with development software, Cypress strongly supports
third-party programmers. All major third-party programmers
support the MAX family.
Cross Reference
ALTERA
PREFIX EPM
PREFIX: EP
22V10–10C
22V10–10C
22V10–10C
22V10–10C
22V10–15C
22V10–15C
5032DC
5032DC–2
5032DC–15
5032DC–17
5032DC–20
5032DC–25
5032DM
5032DM–25
5032JC
5032JC–2
5032JC–15
5032JC–17
5032JC–20
CYPRESS
PREFIX: CY
PREFIX: PALC
PALC22V10D–7C
PALC22V10D–10C
PAL22V10C–7C+
PAL22V10C–10C+
PALC22V10B–15C
PALC22V10D–15C
7C344–25WC
7C344–20WC
7C344–15WC
Call Factory
7C344–20WC
7C344–25WC
7C344–25WMB
7C344–25WMB
7C344–25HC
7C344–20HC
7C344–15HC
Call Factory
7C344–20HC
Development Software Support
Warp
Warp is a state-of-the-art compiler and complete CPLD design
tool. For design entry,
Warp
provides an IEEE-STD-1076/1164
VHDL text editor, an IEEE-STD-1364 Verilog text editor and a
graphical finite state machine editor. It provides optimized syn-
thesis and fitting by replacing basic circuits with ones pre-op-
timized for the target device, by implementing logic in unused
memory and by perfect communication between fitting and
synthesis.
Warp
provides other tools such as graphical timing
simulation and analysis.
Warp
Professional
Warp
Professional contains several additional features. It pro-
vides an extra method of design entry with its graphical block
diagram editor. It allows up to 5 ms timing simulation instead
of only 2 ms. It allows comparing of waveforms before and after
design changes.
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
