74LVT573 • 74LVTH573 Low Voltage Octal Transparent Latch with 3-STATE Outputs
March 1999
Revised March 2005
74LVT573 • 74LVTH573
Low Voltage Octal Transparent Latch
with 3-STATE Outputs
General Description
The LVT573 and LVTH573 consist of eight latches with
3-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch
Enable (LE) is HIGH. When LE is low, the data satisfying
the input timing requirements is latched. Data appears on
the bus when the Output Enable (OE) is LOW. When OE is
HIGH, the bus output is in the high impedance state.
The LVTH573 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These octal latches are designed for low-voltage (3.3V)
V
CC
applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT573 and LVTH573
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining a low power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH573),
also available without bushold feature (74LVT573)
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs source/sink
32 mA/
64 mA
s
Functionally compatible with the 74 series 573
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human-body model
!
2000V
Machine model
!
200V
Charged-device model
!
1000V
Ordering Code:
Order Number
74LVT573WM
74LVT573SJ
74LVT573MSA
74LVT573MTC
74LVT573MTCX_NL
(Note 1)
74LVTH573WM
74LVTH573SJ
74LVTH573MSA
74LVTH573MTC
74LVTH573MTCX_NL
(Note 1)
Package
Number
M20B
M20D
MSA20
MTC20
MTC20
M20B
M20D
MSA20
MTC20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS012450
www.fairchildsemi.com
74LVT573 • 74LVTH573
Logic Symbols
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
Description
IEEE/IEC
O
0
–O
7
Truth Table
Inputs
LE
X
H
H
OE
H
L
L
L
D
n
X
L
H
X
Outputs
O
n
Z
L
H
O
0
Connection Diagram
H
L
Z
X
O
0
L
HIGH Voltage Level
LOW Voltage Level
High Impedance
Immaterial
Previous O
0
before HIGH to LOW transition of Latch Enable
Functional Description
The LVT573 and LVTH573 contain eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input
is HIGH, data on the D
n
inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will
change state each time its D-type input changes. When LE is LOW, the latches store the information that was present on
the D-type inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled
by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74LVT573 • 74LVTH573
Absolute Maximum Ratings
(Note 2)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
Conditions
Units
V
V
Output in 3-STATE
Output in High or Low State (Note 3)
V
I
GND
V
O
GND
V
O
!
V
CC
Output at High State
V
O
!
V
CC
Output at Low State
V
mA
mA
mA
mA
mA
0.5 to
4.6
0.5 to
7.0
0.5 to
7.0
0.5 to
7.0
50
50
64
128
r
64
r
128
65 to
150
q
C
Recommended Operating Conditions
Symbol
V
CC
V
I
I
OH
I
OL
T
A
Supply Voltage
Input Voltage
High-Level Output Current
Low-Level Output Current
Free-Air Operating Temperature
Input Edge Rate, V
IN
0.8V–2.0V, V
CC
3.0V
Parameter
Min
2.7
0
Max
3.6
5.5
Units
V
V
mA
mA
32
64
40
0
85
10
q
C
ns/V
'
t/
'
V
Note 2:
Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 3:
I
O
Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
2.7
2.7–3.6
2.7–3.6
2.7–3.6
2.7
3.0
V
OL
Output LOW Voltage
2.7
2.7
3.0
3.0
3.0
I
I(HOLD)
(Note 5)
I
I(OD)
(Note 5)
I
I
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
I
OFF
I
PU/PD
I
OZL
I
OZH
Power Off Leakage Current
Power Up/Down 3-STATE
Output Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3.6
3.6
3.6
0
0–1.5V
3.6
3.6
3.0
Bushold Input Minimum Drive
3.0
75
V
CC
0.2
2.4
2.0
0.2
0.5
0.4
0.5
0.55
V
V
2.0
0.8
T
A
Min
40
q
C to
85
q
C
Typ
(Note 4)
Max
Units
Conditions
V
IK
V
IH
V
IL
V
OH
Input Clamp Diode Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
1.2
V
V
V
I
I
18 mA
V
O
d
0.1V or
V
O
t
V
CC
0.1V
I
OH
I
OH
I
OH
I
OL
I
OL
I
OL
I
OL
I
OL
V
I
V
I
100
P
A
8 mA
32 mA
100
P
A
24 mA
16 mA
32 mA
64 mA
0.8V
2.0V
75
500
P
A
P
A
10
(Note 6)
(Note 7)
V
I
5.5V
0V or V
CC
0V
V
CC
0.5V to 3.0V
GND or V
CC
0.5V
3.0V
V
I
V
I
V
I
500
r
1
5
1
P
A
r
100
r
100
5
5
P
A
P
A
P
A
P
A
0V
d
V
I
or V
O
d
5.5V
V
O
V
I
V
O
V
O
3
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74LVT573 • 74LVTH573
DC Electrical Characteristics
Symbol
I
OZH
I
CCH
I
CCL
I
CCZ
I
CCZ
Parameter
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
Increase in Power Supply Current
(Note 8)
Note 4:
All typical values are at V
CC
3.3V, T
A
25
q
C.
Note 5:
Applies to bushold versions only (74LVTH573).
(Continued)
T
A
Min
V
CC
(V)
3.6
3.6
3.6
3.6
3.6
3.6
40
q
C to
85
q
C
Typ
(Note 4)
10
0.19
5
0.19
0.19
0.2
Max
Units
Conditions
V
CC
V
O
d
5.5V
Outputs HIGH
Outputs LOW
Outputs Disabled
V
CC
d
V
O
d
5.5V,
Outputs Disabled
One Input at V
CC
0.6V
Other Inputs at V
CC
or GND
P
A
mA
mA
mA
mA
mA
'
I
CC
Note 6:
An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7:
An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8:
This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
Dynamic Switching Characteristics
Symbol
V
OLP
V
OLV
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
V
CC
(V)
3.3
3.3
(Note 9)
T
A
Min
25
q
C
Typ
0.8
Max
Units
V
V
Conditions
C
L
50 pF, R
L
500
:
(Note 10)
(Note 10)
0.8
Note 9:
Characterized in SOIC package. Guaranteed parameter, but not tested.
Note 10:
Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
T
A
40
q
C to
85
q
C
C
L
50 pF, R
L
500
:
Symbol
Parameter
Min
t
PHL
t
PLH
t
PHL
t
PLH
t
PZL
t
PZH
t
PLZ
t
PHZ
t
S
t
H
t
W
t
OSHL
t
OSLH
Note 11:
All typical values are at V
CC
3.3V, T
A
25
q
C.
V
CC
3.3V
r
0.3V
Typ
(Note 11)
Max
4.4
4.1
4.4
4.4
5.1
5.1
4.6
4.9
Min
1.5
1.5
1.9
1.9
1.5
1.5
2.0
2.0
0.6
1.7
3.0
1.0
1.0
V
CC
2.7V
Max
4.9
4.7
4.9
5.0
6.6
5.9
4.9
5.5
Units
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Output Enable Time
Output Disable Time
Setup Time, D
n
to LE
Hold Time, D
n
to LE
LE Pulse Width
Output to Output Skew (Note 12)
1.5
1.5
1.9
1.9
1.5
1.5
2.0
2.0
0.7
1.5
3.0
ns
ns
ns
ns
ns
ns
ns
1.0
1.0
ns
Note 12:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Capacitance
(Note 13)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
V
CC
V
CC
Open, V
I
3.0V, V
O
Conditions
0V or V
CC
0V or V
CC
Typical
4
6
Units
pF
pF
Note 13:
Capacitance is measured at frequency f
1 MHz, per MIL-STD-883, Method 3012.
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4
74LVT573 • 74LVTH573
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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