82C59ARP
R
ADIATION
H
ARDENED
Vcc
RD
WR
A0
INTA
CS
D7
CMOS P
RIORITY
I
NTERRUPT
C
ONTROLLER
INTA
INT
DATA BUS
BUFFER
4
3
2
1
28
27
26
D
7
- D
0
CONTROL LOGIC
D6
D5
D4
D3
D2
D1
D0
5
6
7
8
9
10
11
25
24
IR7
IR6
IR5
IR4
IR3
IR2
IR1
RD
WR
A
0
CS
CAS 0
CAS 2
CASCADE
BUFFER
COMPARATOR
SEi
82C59ARP
Top View
23
22
21
20
19
READ/WRITE
LOGIC
IN
SERVICE
REG
(ISR)
PRIORITY
RESOLVER
INTERRUPT
REQUEST
REG
(IRR)
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
12
13
14
15
16
17
18
SP/EN
CAS0
CAS1
GND
CAS2
INT
IR0
INTERRUPT MASK REG
(IMR)
CAS 3
SP/EN
INTERNAL BUS
F
EATURES
:
•
•
•
•
Eight-level Priority Interrupt Controller
R
AD
-P
AK
®
radiation-hardened against natural space radiation
Total dose hardness: > 100 krad (Si); dependent upon orbit
Single event effect:
- SEL
TH
LET: > 80 MeV/mg/cm
2
- SEU
TH
LET: 11.4 MeV/mg/cm
2
Package:
- 28-pin R
AD
-P
AK
®
quad flat pack
Low standby power < 10mA
Expandable to 64-level priority controller
Programmable interrupt modes
80C86 compatible operation
Fully static design
Single 5V power supply
D
ESCRIPTION
:
Space Electronics’ 82C59ARP (RP for R
AD
-P
AK
®
) high-speed microcircuit features a
typical 100 kilorad (Si) total dose tolerance; dependent upon orbit. Using SEi's ra-
diation-hardened R
AD
-P
AK
®
packaging technology, the 82C59ARP is a high-perfor-
mance Priority Interrupt Controller. The 82C59ARP is designed to relieve the system
CPU from the task of polling in a multi-level priority interrupt system. It can handle
up to eight vectored priority interrupting sources and is cascadable to 64 without
additional circuitry. Individual interrupting sources can be masked or prioritized to
allow custom system configuration. The fully static circuit design, requiring no clock
input, ensures low operating power. Capable of surviving space environments, the
82C59ARP is ideal for satellite, spacecraft, and space probe missions. SEi's R
AD
-P
AK
®
advanced technology incorporates radiation shielding in the microcircuit package.
It eliminates box shielding while providing required lifetime in orbit. It is available
with packaging and screening up to Class S.
•
•
•
•
•
•
•
0115.99Rev0
Specification and design are subject to change without notice.
1
--8.13--
©1998 Space Electronics Inc.
All rights reserved
82C59ARP
R
ADIATION
H
ARDENED
PARAMETER
Supply Voltage
Input, Output or I/O Voltage
Storage Temperature Range
Power Dissipation
CMOS P
RIORITY
I
NTERRUPT
C
ONTROLLER
82C59ARP ABSOLUTE MAXIMUM RATINGS
SYMBOL
MIN
MAX
V
SS
+8.0
GND-0.5V
V
CC
+0.5
T
s
-65
+150
P
D
1
UNITS
V
V
°
C
W
PARAMETER
Logical One
Input Voltage
Logical Zero
Input Voltage
Output HIGH Voltage
Output LOW Voltage
Input Leakage Current
Output Leakage Current
IR Input Load Current
82C59ARP DC ELECTRICAL CHARACTERISTICS
TEST CONDITIONS
SYMBOL
MIN
V
lH
2.0
2.2
V
IL
I
OH
= -2.5mA
l
OH
=
-100
µ
A
l
OL
= +2.5mA
V
IN
= GND or V
CC
V
OUT
= GND or V
CC
V
IN
= 0V
V
IN
=
V
CC
All temperature ranges
V
CC
= 5.5V
V
IN
= V
CC
or GND
Outputs Open
V
CC
= 5.0V
V
IN
= V
CC
or GND
Outputs Open
T
A
= 25
°
C
V
OH
V
OL
I
I
I
O
I
LIR
3.0
V
CC
- 0.4
-1.0
-10.0
MAX
UNITS
V
V
V
0.8
0.4
+1.0
+10.0
-200
10
10
V
µ
A
µ
A
µ
A
µ
A
µ
A
Standby Power Supply Current
l
CCSB
Operating Power Supply Current
I
CCOP
1
m
A/MHz
82C59ARP CAPACITANCE
(T
A
= 25
o
C)
PARAMETER
Input Capacitance
Output Capacitance
I/O Capacitance
SYMBOL
C
IN
C
OUT
C
I/O
TYPICAL
15
15
15
UNITS
pF
pF
pF
0115.99Rev0
Specification and design are subject to change without notice.
2
--8.13--
©1998 Space Electronics Inc.
All rights reserved
82C59ARP
R
ADIATION
H
ARDENED
CMOS P
RIORITY
I
NTERRUPT
C
ONTROLLER
82C59ARP AC CHARATERISTICS
(V
CC
= +5.0V ± 10%, GND =0V, T
A
= -55
°
C to +125
°
C, unless otherwise specified)
TIMING REQUIREMENTS
PARAMETER
A0/CS Setup to RD/INTA
A0/CS Hold after RD/INTA
RD/INTA Pulse Width
A0/CS Setup to WR
A0/CS Hold after WR
WR Pulse Width
Data Setup to WR
Data Hold after WR
Interrupt Request Width Low
Cascade Setup to Second or Third INTA (Slave
Only)
End of RD to next RD, End of INTA to next
INTA (within an INTA sequence only)
End of WR to next WR
End of Command to next command (not same
command type), End of INTA sequence to next
INTA sequence
SYMBOL
(1) T
AHRL
(2) T
RHAX
(3) T
RLRH
(4) T
AHWL
(5) T
WHAX
(6) T
WLWH
(7) T
DVWH
(8) T
WHDX
(9) T
JLJH
(10) T
CVlAL
(11) T
RHRL
(12) T
WHWL
(13) T
CHCL
82C59ARP-5
MIN
MAX
10
-
5
-
235
-
0
-
5
-
165
-
240
-
5
-
100
-
55
-
160
190
500
-
-
-
82C59ARP-8
MIN
MAX
10
-
5
-
160
-
0
-
5
-
95
-
160
-
5
-
100
-
40
-
160
190
400
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING RESPONSES
PARAMETER
Data Valid from RD/INTA
Data Float after RD/INTA
Interrupt Output Delay
Cascade Valid from First INTA (Master Only)
Enable Active from RD or INTA
Enable Inactive from RD or INTA
Data Valid from Stable Address
Cascade Valid to Valid Data
SYMBOL
(14) T
RLDV
(15) T
RHDZ
(16) T
JHlH
(17) T
lALCV
(18) T
RLEL
(19) T
RHEH
(20) T
AHDV
(21) T
CVDV
82C59ARP-5
MIN
MAX
-
160
5
100
-
350
-
565
-
125
-
60
-
210
-
300
82C59ARP-8
MIN
MAX
-
120
5
85
-
300
-
360
-
100
-
50
-
200
-
200
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
0115.99Rev0
Specification and design are subject to change without notice.
3
--8.13--
©1998 Space Electronics Inc.
All rights reserved
82C59ARP
R
ADIATION
H
ARDENED
CMOS P
RIORITY
I
NTERRUPT
C
ONTROLLER
0115.99Rev0
Specification and design are subject to change without notice.
4
--8.13--
©1998 Space Electronics Inc.
All rights reserved
82C59ARP
R
ADIATION
H
ARDENED
CMOS P
RIORITY
I
NTERRUPT
C
ONTROLLER
0115.99Rev0
Specification and design are subject to change without notice.
5
--8.13--
©1998 Space Electronics Inc.
All rights reserved
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
