3-STATE standard outputs. The device is byte controlled
with each byte functioning identically, but independent of
the other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LE
n
) input is HIGH, data on
the I
n
enters the latches. In this condition the latches are
transparent, i.e. a latch output will change state each time
its I input changes. When LE
n
is LOW, the latches store
information that was present on the I inputs a setup time
preceding the HIGH-to-LOW transition of LE
n
. The
3-STATE standard outputs are controlled by the Output
Enable (OE
n
) input. When OE
n
is LOW, the standard out-
puts are in the 2-state mode. When OE
n
is HIGH, the stan-
dard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.
Logic Diagrams
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
www.fairchildsemi.com
74LCX16373
Absolute Maximum Ratings
(Note 4)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
Conditions
Units
V
V
Output in 3-STATE
Output in HIGH or LOW State (Note 5)
V
I
GND
V
O
GND
V
O
!
V
CC
V
mA
mA
mA
mA
mA
0.5 to
7.0
0.5 to
7.0
0.5 to
7.0
0.5 to V
CC
0.5
50
50
50
r
50
r
100
r
100
65 to
150
q
C
Recommended Operating Conditions
(Note 6)
Symbol
V
CC
V
I
V
O
I
OH
/I
OL
Supply Voltage
Input Voltage
Output Voltage
Output Current
HIGH or LOW State
3-STATE
V
CC
V
CC
V
CC
T
A
Free-Air Operating Temperature
Input Edge Rate, V
IN
0.8V–2.0V, V
CC
3.0V
3.0V
3.6V
2.7V
3.0V
2.3V
2.7V
Parameter
Operating
Data Retention
Min
2.0
1.5
0
0
0
Max
3.6
3.6
5.5
V
CC
5.5
Units
V
V
V
r
24
r
12
r
8
40
0
85
10
mA
q
C
ns/V
'
t/
'
V
Note 4:
The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 5:
I
O
Absolute Maximum Rating must be observed.
Note 6:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
I
OH
I
OH
I
OH
I
OH
I
OH
V
OL
LOW Level Output Voltage
I
OL
I
OL
I
OL
I
OL
I
OL
I
I
I
OZ
I
OFF
Input Leakage Current
3-STATE Output Leakage
Power-Off Leakage Current
Conditions
V
CC
(V)
2.3
2.7
2.7
3.6
2.3
2.7
2.7
3.6
T
A
40
q
C to
85
q
C
Max
Min
1.7
2.0
Units
V
0.7
0.8
V
CC
0.2
1.8
2.2
2.4
2.2
0.2
0.6
0.4
0.4
0.55
V
100
P
A
8 mA
2.3
3.6
2.3
2.7
3.0
3.0
2.3
3.6
2.3
2.7
3.0
3.0
2.3
3.6
2.3
3.6
0
12 mA
18 mA
24 mA
100
P
A
8 mA
12 mA
16 mA
24 mA
V
V
0
d
V
I
d
5.5V
0
d
V
O
d
5.5V
V
I
V
IH
or V
IL
5.5V
V
I
or V
O
r
5.0
r
5.0
10
P
A
P
A
P
A
www.fairchildsemi.com
4
74LCX16373
DC Electrical Characteristics
Symbol
I
CC
Parameter
Quiescent Supply Current
Increase in I
CC
per Input
V
I
V
IH
(Continued)
V
CC
(V)
V
CC
or GND
V
CC
0.6V
2.3
3.6
2.3
3.6
2.3
3.6
T
A
Conditions
40
q
C to
85
q
C
Max
20
Units
Min
3.6V
d
V
I
, V
O
d
5.5V (Note 7)
r
20
500
P
A
P
A
'
I
CC
Note 7:
Outputs disabled or 3-STATE only.
AC Electrical Characteristics
T
A
Symbol
Parameter
V
CC
C
L
Min
t
PHL
t
PLH
t
PHL
t
PLH
t
PZL
t
PZH
t
PLZ
t
PHZ
t
S
t
H
t
W
t
OSHL
t
OSLH
Setup Time, I
n
to LE
Hold Time, I
n
to LE
LE Pulse Width
Output to Output Skew (Note 8)
Output Disable Time
Propagation Delay
I
n
to O
n
Propagation Delay
LE to O
n
Output Enable Time
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
1.5
3.0
1.0
1.0
3.3V
r
0.3V
50 pF
Max
5.4
5.4
5.5
5.5
6.1
6.1
6.0
6.0
40
q
C to
85
q
C, R
L
V
CC
C
L
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
1.5
3.0
2.7V
50 pF
Max
5.9
5.9
6.4
6.4
6.5
6.5
6.3
6.3
500
:
V
CC
C
L
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
3.0
2.0
3.5
2.5V
r
0.2V
30 pF
Max
6.5
6.5
6.6
6.6
7.9
7.9
7.2
7.2
ns
ns
ns
ns
ns
ns
ns
ns
Units
Note 8:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
