电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

IDT71V67603S150BG8

产品描述Cache SRAM, 256KX36, 3.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
产品类别存储    存储   
文件大小984KB,共23页
制造商IDT (Integrated Device Technology)
下载文档 详细参数 选型对比 全文预览

IDT71V67603S150BG8概述

Cache SRAM, 256KX36, 3.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

IDT71V67603S150BG8规格参数

参数名称属性值
是否无铅含铅
是否Rohs认证不符合
厂商名称IDT (Integrated Device Technology)
零件包装代码BGA
包装说明BGA, BGA119,7X17,50
针数119
Reach Compliance Codenot_compliant
ECCN代码3A991.B.2.A
最长访问时间3.8 ns
其他特性PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)150 MHz
I/O 类型COMMON
JESD-30 代码R-PBGA-B119
JESD-609代码e0
长度22 mm
内存密度9437184 bit
内存集成电路类型CACHE SRAM
内存宽度36
湿度敏感等级3
功能数量1
端子数量119
字数262144 words
字数代码256000
工作模式SYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织256KX36
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码BGA
封装等效代码BGA119,7X17,50
封装形状RECTANGULAR
封装形式GRID ARRAY
并行/串行PARALLEL
峰值回流温度(摄氏度)225
电源3.3 V
认证状态Not Qualified
座面最大高度2.36 mm
最大待机电流0.05 A
最小待机电流3.14 V
最大压摆率0.305 mA
最大供电电压 (Vsup)3.465 V
最小供电电压 (Vsup)3.135 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Lead (Sn63Pb37)
端子形式BALL
端子节距1.27 mm
端子位置BOTTOM
处于峰值回流温度下的最长时间20
宽度14 mm
Base Number Matches1

文档预览

下载PDF文档
256K X 36, 512K X 18
3.3V Synchronous SRAMs
3.3V I/O, Burst Counter
Pipelined Outputs, Single Cycle Deselect
x
x
IDT71V67603
IDT71V67803
Features
256K x 36, 512K x 18 memory configurations
Supports high system speed:
– 166MHz 3.5ns clock access time
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
LBO
input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW byte
GW),
GW
write enable (BWE and byte writes (BW
BWE),
BWx)
BWE
BW
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O supply (V
DDQ
)
Packaged in a JEDEC Standard 100-pin thin plastic quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA).
x
x
x
x
x
x
Description
The IDT71V67603/7803 are high-speed SRAMs organized as
256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write,
data, address and control registers. Internal logic allows the SRAM to
generate a self-timed write based upon a decision which can be left until
the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V67603/7803 can provide four cycles of
data for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the
LBO
input pin.
The IDT71V67603/7803 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-
pin thin plastic quad flatpack (TQFP), a 119 ball grid array (BGA) and a 165
fine pitch ball grid array (fBGA).
Pin Description Summary
A
0
-A
18
CE
CS
0
,
CS
1
OE
GW
BWE
BW
1
,
BW
2
,
BW
3
,
BW
4
(1)
CLK
ADV
ADSC
ADSP
LBO
ZZ
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
V
DD
, V
DDQ
V
SS
Address Inputs
Chip Enable
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
N/A
N/A
5310 tbl 01
NOTE:
1.
BW
3
and
BW
4
are not applicable for the IDT71V67802.
SEPTEMBER 2004
1
©2004 Integrated Device Technology, Inc.
DSC-5310/06

IDT71V67603S150BG8相似产品对比

IDT71V67603S150BG8 IDT71V67803S133PFGI8 IDT71V67803S166BG8 IDT71V67803S150BG8 IDT71V67803S133BG8 IDT71V67603S133BGI8 IDT71V67603S133PFG8 IDT71V67603S150BGI8 IDT71V67603S133BG8 IDT71V67803S133PFG8
描述 Cache SRAM, 256KX36, 3.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119 Cache SRAM, 512KX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 Cache SRAM, 512KX18, 3.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119 Cache SRAM, 512KX18, 3.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119 Cache SRAM, 512KX18, 4.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119 Cache SRAM, 256KX36, 4.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119 Cache SRAM, 256KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 Cache SRAM, 256KX36, 3.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119 Cache SRAM, 256KX36, 4.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119 Cache SRAM, 512KX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
是否无铅 含铅 不含铅 含铅 含铅 含铅 含铅 不含铅 含铅 含铅 不含铅
是否Rohs认证 不符合 符合 不符合 不符合 不符合 不符合 符合 不符合 不符合 符合
零件包装代码 BGA QFP BGA BGA BGA BGA QFP BGA BGA QFP
包装说明 BGA, BGA119,7X17,50 LQFP, QFP100,.63X.87 BGA, BGA119,7X17,50 BGA, BGA119,7X17,50 BGA, BGA119,7X17,50 BGA, BGA119,7X17,50 LQFP, QFP100,.63X.87 BGA, BGA119,7X17,50 BGA, BGA119,7X17,50 LQFP, QFP100,.63X.87
针数 119 100 119 119 119 119 100 119 119 100
Reach Compliance Code not_compliant compliant not_compliant not_compliant not_compliant not_compliant compliant not_compliant not_compliant compliant
ECCN代码 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A
最长访问时间 3.8 ns 4.2 ns 3.5 ns 3.8 ns 4.2 ns 4.2 ns 4.2 ns 3.8 ns 4.2 ns 4.2 ns
其他特性 PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE
最大时钟频率 (fCLK) 150 MHz 133 MHz 166 MHz 150 MHz 133 MHz 133 MHz 133 MHz 150 MHz 133 MHz 133 MHz
I/O 类型 COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON
JESD-30 代码 R-PBGA-B119 R-PQFP-G100 R-PBGA-B119 R-PBGA-B119 R-PBGA-B119 R-PBGA-B119 R-PQFP-G100 R-PBGA-B119 R-PBGA-B119 R-PQFP-G100
JESD-609代码 e0 e3 e0 e0 e0 e0 e3 e0 e0 e3
长度 22 mm 20 mm 22 mm 22 mm 22 mm 22 mm 20 mm 22 mm 22 mm 20 mm
内存密度 9437184 bit 9437184 bit 9437184 bit 9437184 bit 9437184 bit 9437184 bit 9437184 bit 9437184 bit 9437184 bit 9437184 bit
内存集成电路类型 CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM
内存宽度 36 18 18 18 18 36 36 36 36 18
湿度敏感等级 3 3 3 3 3 3 3 3 3 3
功能数量 1 1 1 1 1 1 1 1 1 1
端子数量 119 100 119 119 119 119 100 119 119 100
字数 262144 words 524288 words 524288 words 524288 words 524288 words 262144 words 262144 words 262144 words 262144 words 524288 words
字数代码 256000 512000 512000 512000 512000 256000 256000 256000 256000 512000
工作模式 SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
最高工作温度 70 °C 85 °C 70 °C 70 °C 70 °C 85 °C 70 °C 85 °C 70 °C 70 °C
组织 256KX36 512KX18 512KX18 512KX18 512KX18 256KX36 256KX36 256KX36 256KX36 512KX18
输出特性 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 BGA LQFP BGA BGA BGA BGA LQFP BGA BGA LQFP
封装等效代码 BGA119,7X17,50 QFP100,.63X.87 BGA119,7X17,50 BGA119,7X17,50 BGA119,7X17,50 BGA119,7X17,50 QFP100,.63X.87 BGA119,7X17,50 BGA119,7X17,50 QFP100,.63X.87
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 GRID ARRAY FLATPACK, LOW PROFILE GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY FLATPACK, LOW PROFILE GRID ARRAY GRID ARRAY FLATPACK, LOW PROFILE
并行/串行 PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
峰值回流温度(摄氏度) 225 260 225 225 225 225 260 225 225 260
电源 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 2.36 mm 1.6 mm 2.36 mm 2.36 mm 2.36 mm 2.36 mm 1.6 mm 2.36 mm 2.36 mm 1.6 mm
最大待机电流 0.05 A 0.07 A 0.05 A 0.05 A 0.05 A 0.07 A 0.05 A 0.07 A 0.05 A 0.05 A
最小待机电流 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V
最大压摆率 0.305 mA 0.28 mA 0.34 mA 0.305 mA 0.26 mA 0.28 mA 0.26 mA 0.325 mA 0.26 mA 0.26 mA
最大供电电压 (Vsup) 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V
最小供电电压 (Vsup) 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V
标称供电电压 (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
表面贴装 YES YES YES YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 COMMERCIAL INDUSTRIAL COMMERCIAL COMMERCIAL COMMERCIAL INDUSTRIAL COMMERCIAL INDUSTRIAL COMMERCIAL COMMERCIAL
端子面层 Tin/Lead (Sn63Pb37) Matte Tin (Sn) - annealed Tin/Lead (Sn63Pb37) Tin/Lead (Sn63Pb37) Tin/Lead (Sn63Pb37) Tin/Lead (Sn63Pb37) Matte Tin (Sn) - annealed Tin/Lead (Sn63Pb37) Tin/Lead (Sn63Pb37) Matte Tin (Sn) - annealed
端子形式 BALL GULL WING BALL BALL BALL BALL GULL WING BALL BALL GULL WING
端子节距 1.27 mm 0.65 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm 0.65 mm 1.27 mm 1.27 mm 0.65 mm
端子位置 BOTTOM QUAD BOTTOM BOTTOM BOTTOM BOTTOM QUAD BOTTOM BOTTOM QUAD
处于峰值回流温度下的最长时间 20 30 20 20 20 20 30 20 20 30
宽度 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm
厂商名称 IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) - - IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Base Number Matches 1 1 1 1 1 1 1 - - -
有奖直播:TI 芯技术助力电机开发 进行中!
有奖直播:TI 芯技术助力电机开发 进行中! >>点击进入直播 直播时间: 2022年9月9日(周五)上午10:00 直播主题: TI 芯技术助力电机开发 直播介绍: 本次 ......
EEWORLD社区 TI技术论坛
NAND闪存的写入限制与发展
在过去的三年中,咨询公司以及一些业界机构一直都对NAND闪存能否在一段时间内持续处理大量写入操作持有怀疑态度,而这也就是我们一直所说的NAND写入的限制问题,而这些疑问最终则引起了人们对NA ......
wxycqp PCB设计
放大器和转换器模拟设计技巧 ——TI 专家Bonnie Baker
《放大器和转换器模拟设计技巧》,主要针对模拟电路设计中会由放大器和转换器产生的问题,及其针对这些问题的设计技巧和解决方案做出了详细的说明,相信一定对工程师朋友们有很大帮助。 《放大 ......
maylove 模拟与混合信号
给Android制造补丁升级包
本帖最后由 Wince.Android 于 2015-3-18 08:44 编辑 是这样的,我的Android先前已经发布了一个Android20150312.tar.bz2的1.7G的包了,但是过了几天我改了一些东西升级成Android20150316.tar. ......
Wince.Android 嵌入式系统
秀一秀你焊过的最变态的电路板
我先上一个,今天赋闲在家收拾零碎的时候发现的,大二的时候焊的,用8-3线编码器和二极管组成了一个16-4线编码器,加上四个独立按键,组成了一个20键的键盘。 91465 91466 91467 现在也搞不 ......
柳叶舟 PCB设计

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 2122  406  840  1753  2309  48  43  19  40  31 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved