74ACT11478
METASTABLE RESISTAND OCTAL D TYPE DUAL RANK FLIP FLOP
WITH 3-STATE OUTPUTS
•
•
•
•
•
•
•
•
•
Inputs Are TTL-Voltage Compatible
Specifically Designed for Data
Synchronization Applications
Improved Metastable Characteristics
Provide Greater System Reliability
3-State Outputs Drive Bus Lines Directly
Flow-Through Architecture to Optimize
PCB Layout
Center-Pin V
CC
and GND Configurations to
Minimize High-Speed Switching Noise
EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity
at 125°C
Package Options Include Plastic Small
Outline Packages and Standard Plastic
300-mil DIPs
DW OR NT PACKAGE
(TOP VIEW)
SCAS131 − APRIL 1990 − REVISED APRIL 1993
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
1D
2D
3D
4D
V
CC
V
CC
5D
6D
7D
8D
CLK
description
The 74ACT11478 is an 8-bit dual-rank synchronizer circuit designed specifically for data synchronization
applications where the normal setup and hold time specifications are frequently violated.
Synchronization of two digital signals operating at different frequencies is a common system problem. This
problem is typically solved by synchronizing one of the signals to the local clock through a flip-flop. This solution,
however, causes the setup and hold time specifications associated with the flip-flop to be violated. When the
setup or hold time specification is violated, the output response is uncertain.
A flip-flop is metastable if its output hangs up in the region between V
IL
and V
IH
. The metastable condition lasts
until the flip-flop recovers into one of its two stable states. With conventional flip-flops, this recovery time can
be longer than the specified maximum propagation delay.
The problem of metastability is typically solved by adding an additional layer of synchronization. This type of
dual ranking is employed in the 74ACT11478. The probability of the second stage entering the metastable state
is exponentially reduced by this dual-rank architecture. The 74ACT11478 provides a one-chip solution for
system designers in asynchronous applications.
The 74ACT11478 is characterized for operation from − 40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
H
L
L
L
CLOCK†
X
↑
↑
H
D
X
L
H
X
OUTPUT
Q
Z
L
H
QO
† Data presented at the D input requires two
clock cycles to appear at the Q output.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1993, Texas Instruments Incorporated
POST OFFICE BOX 655303
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251−1443
•
DALLAS, TEXAS 75265
1
SCAS131 − APRIL 1990 − REVISED APRIL 1993
74ACT11478
METASTABLE RESISTAND OCTAL D TYPE DUAL RANK FLIP FLOP
WITH 3-STATE OUTPUTS
logic symbol
†
logic diagram (positive logic)
24
13
23
1D
1
1Q
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
24
13
23
22
21
20
17
16
15
14
EN
C1
OE
CLK
1D
1D
1
2
3
4
9
10
11
12
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
C1
1D
C1
To Seven Other Flip-Flops
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to V
CC
+ 0.5 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
20 mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
50 mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
50 mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
MIN
VCC
VIH
VIL
VI
VO
IOH
IOL
D
t/Dv
TA
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
0
− 40
0
0
4.5
2
0.8
VCC
VCC
− 24
24
10
85
MAX
5.5
UNIT
V
V
V
V
V
mA
mA
ns /V
°C
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
74ACT11478
METASTABLE RESISTAND OCTAL D TYPE DUAL RANK FLIP FLOP
WITH 3-STATE OUTPUTS
SCAS131 − APRIL 1990 − REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
IOH = − 50
mA
A
VOH
IOH = − 24 mA
IOH = − 75 mA
{
IOL = 50
mA
A
VOL
IOL = 24 mA
IOL = 75 mA
{
IOZ
II
ICC
DI
CC‡
Ci
Co
VO = VCC or GND
VI = VCC or GND
VI = VCC or GND,
IO = 0
One input at 3.4 V,
Other inputs at GND or VCC
VI = VCC or GND
VO = VCC or GND
TEST CONDITIONS
VCC
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5V
5V
4.5
12
±
0.5
±
0.1
8
0.9
0.1
0.1
0.36
0.36
TA = 25°C
MIN
TYP
MAX
4.4
5.4
3.94
4.94
MIN
4.4
5.4
3.8
4.8
3.85
0.1
0.1
0.44
0.44
1.65
±
5
±
1
80
1
mA
mA
mA
mA
pF
pF
V
V
MAX
UNIT
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
MIN
0
4
5
2.7
1.5
ns
ns
ns
MAX
75
UNIT
MHz
f
clock
tw
tsu
th
Clock frequency
CLK high
Pulse duration
Setup time, data before CLK↑
Hold time, data after CLK↑
CLK low
0
4
5
2.7
1.5
75
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
MIN
TYP
MAX
7.5
4.3
CLK
OE
OE
Q
Q
Q
5.6
3.7
4.7
4.4
4.7
7.4
9.4
7.5
9.2
7.2
6.6
10.1
12.6
11.1
13.7
9.2
8.7
MIN
75
4.3
5.6
3.7
4.7
4.4
4.7
11.6
14.2
12.6
15.8
9.8
9.3
ns
ns
ns
MAX
UNIT
MHz
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
3
SCAS131 − APRIL 1990 − REVISED APRIL 1993
74ACT11478
METASTABLE RESISTAND OCTAL D TYPE DUAL RANK FLIP FLOP
WITH 3-STATE OUTPUTS
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER
Outputs enabled
Cpd
Power dissipation capacitance per flip-flop
Outputs disabled
CL = 50 pF,
f = 1 MHz
TEST CONDITIONS
TYP
76
64
pF
UNIT
PARAMETER MEASUREMENT INFORMATION
2 X VCC
From Output
Under Test
CL = 50 pF
(see Note A)
500
Ω
S1
Open
GND
500
Ω
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2 x VCC
GND
LOAD CIRCUIT
3V
1.5 V
0V
tsu
Data
Input
1.5 V
th
3V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(Low-Level
Enabling)
tPZL
Low-Level
Input
1.5 V
1.5 V
0
VOLTAGE WAVEFORMS
PULSE DURATION
3V
1.5 V
1.5 V
0
tPLZ
tw
3V
3V
1.5 V
1.5 V
0
Timing Input
(see Note B)
High-Level
Input
Input
(see Note B)
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
3V
1.5 V
1.5 V
0
tPHL
VOH
50%
50%
VOL
tPLH
VOH
50%
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
50%
VOL
Output
Waveform 1
S1 at 2 x VCC
(see Note C)
tPZH
Output
Waveform 2
S1 at GND
(see Note C)
≈
VCC
50%
tPHZ
VOH
20%
VOL
50%
80%
≈
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, ZO = 50
Ω,
tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
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