HI5628
NOT RECOMMENDED FOR NEW DESIGNS
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
DATASHEET
FN4520
Rev 5.00
September 2000
8-Bit, 125/60MSPS, Dual High Speed CMOS D/A Converter
The HI5628 is an 8-bit, dual 125MSPS D/A converter which
is implemented in an advanced CMOS process. Operating
from a single +5V to +3V supply, the converter provides
20.48mA of full scale output current and includes an input
data register. Low glitch energy and excellent frequency
domain performance are achieved using a segmented
architecture. The single DAC version is the HI5660 while
10-bit versions exist in the HI5760 and HI5728.
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . 125MSPS
• Low Power . . . . . . . . . . . . . 330mW at 5V, 170mW at 3V
• Integral Linearity Error . . . . . . . . . . . . . . . . . . .
0.25
LSB
• Differential Linearity . . . . . . . . . . . . . . . . . . . . .
0.25
LSB
• Channel Isolation (Typ) . . . . . . . . . . . . . . . . . . . . . . 80dB
• SFDR to Nyquist at 10MHz Output . . . . . . . . . . . . 60dBc
Ordering Information
PART
NUMBER
HI5628IN
HI5628/6IN
HI5628EVAL1
TEMP.
RANGE
(
o
C)
MAX
CLOCK
SPEED
• Internal 1.2V Bandgap Voltage Reference
• Single Power Supply from +5V to +3V
• CMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
PACKAGE
PKG. NO.
-40 to 85 48 Ld LQFP
-40 to 85 48 Ld LQFP
25
Q48.7x7A 125MHz
Q48.7x7A 60MHz
125MHz
Evaluation Platform
Applications
• Direct Digital Frequency Synthesis
• Wireless Communications
• Signal Reconstruction
• Arbitrary Waveform Generators
• Test Equipment
• High Resolution Imaging Systems
Pinout
HI5628 (LQFP)
TOP VIEW
ID7 (MSB)
QD7 (MSB)
QD6
DV
DD
DGND
QCLK
DGND
ICLK
DV
DD
ID4
ID3
ID2
ID1
ID0 (LSB)
DGND
DGND
SLEEP
DV
DD
DGND
NC
AV
DD
48 47 46 45 44 43 42 41 40 39 38 37
36
35
2
34
3
33
4
32
5
31
6
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
1
QD5
ID5
ID6
QD4
QD3
QD2
QD1
QD0 (LSB)
DGND
DGND
DV
DD
DGND
NC
AV
DD
AGND
REFLO
AGND
QOUTB
AGND
ICOMP1
QOUTA
FSADJ
FN4520 Rev 5.00
September 2000
QCOMP1
IOUTB
IOUTA
REFIO
AGND
Page 1 of 10
HI5628
Typical Applications Circuit
I
CLK
/Q
CLK
50
DV
DD
0.1F
DV
DD
0.1F
ANALOG GROUND
PLANE
DIGITAL GROUND
PLANE
ID4
ID3
ID2
ID1
ID0 (LSB)
SLEEP
AGND
DV
DD
0.1F
AV
DD
0.1F
48 47 46 45 44 43 42 41 40 39 38 37
36
1
35
2
34
3
33
4
32
5
DGND 31
6 DGND
DGND 30
7 DGND
DVDD 29
8
DGND 28
9 DVDD
27
NC (GND)
DGND
10
AV
DD
26
11 NC (GROUND)
25
12
13 14 15 16 17 18 19 20 21 22 23 24
AGND
QD7 (MSB)
QD6
QD5
ID5
ID6
ID7 (MSB)
QD4
QD3
QD2
QD1
QD0 (LSB)
DV
DD
PLANE
0.1F
AV
DD
0.1F
AGND
QCOMP1
REFIO
R
SET
1.91k
0.1F
0.1F
AV
DD
AV
DD
ICOMP1
0.1F
50 50
50 50
NOTE: ICOMP1 AND QCOMP1 PINS (24, 14)
MUST BE TIED TOGETHER EXTERNALLY
IOUTA
IOUTB
QOUTB
QOUTA
+5V TO +3V
POWER SUPPLY
FERRITE
BEAD
10H
10F
0.1F
DV
DD
(POWER PLANE)
AV
DD
(POWER PLANE)
FERRITE
BEAD
10H
0.1F
+5V TO +3V (SUPPLY)
+
10F
NOTE: Recommended separate analog and digital ground planes, connected at a single point near the device. See AN9827.
FN4520 Rev 5.00
September 2000
Page 2 of 10
HI5628
Functional Block Diagram
IOUTA
IOUTB
(LSB) ID0
ID1
ID2
ID3
ID4
ID5
ID6
(MSB) ID7
LATCH
UPPER
5-BIT
DECODER
31
LATCH
34
34
CASCODE
CURRENT
SOURCE
SWITCH
MATRIX
3 LSBs
+
31 MSB
SEGMENTS
ICLK
INT/EXT
VOLTAGE
REFERENCE
ICOMP1
INT/EXT
REFERENCE
SELECT
BIAS
GENERATION
REFLO
REFIO
FSADJ
SLEEP
QCOMP1
(LSB) QD0
QD1
QD2
QD3
QD4
QD5
QD6
(MSB) QD7
LATCH
UPPER
5-BIT
DECODER
31
LATCH
34
SWITCH
MATRIX
34
CASCODE
CURRENT
SOURCE
3 LSBs
+
31 MSB
SEGMENTS
QCLK
AV
DD
AGND
DV
DD
DGND
QOUTA QOUTB
FN4520 Rev 5.00
September 2000
Page 3 of 10
HI5628
Absolute Maximum Ratings
Digital Supply Voltage DV
DD
to DCOM . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AV
DD
to ACOM . . . . . . . . . . . . . . . . . +5.5V
Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D7-D0, CLK, SLEEP). . . . . . . . DV
DD
+ 0.3V
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . .
50A
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AV
DD
+ 0.3V
Analog Output Current (I
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Thermal Information
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AV
DD
= +5V, DV
DD
= +5V, V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25
o
C for All Typical Values. Data
given is per channel except for ‘Power Supply Characteristics.’
HI5628IN
T
A
= -40
o
C TO 85
o
C
PARAMETER
SYSTEM PERFORMANCE
(Per Channel)
Resolution
Integral Linearity Error, INL
Differential Linearity Error, DNL
Offset Error, I
OS
Offset Drift Coefficient
Full Scale Gain Error, FSE
TEST CONDITIONS
MIN
TYP
MAX
UNITS
8
“Best Fit” Straight Line (Note 7)
(Note 7)
(Note 7)
(Note 7)
With External Reference (Notes 2, 7)
With Internal Reference (Notes 2, 7)
-0.5
-0.5
-0.025
-
0.25
0.25
-
0.1
2
1
50
100
0.1
80
-
-
-
+0.5
+0.5
+0.025
Bits
LSB
LSB
% FSR
ppm
FSR/
o
C
-
-10
-10
-
-
-0.5
-
+10
+10
-
-
0.5
-
1.25
20
% FSR
% FSR
ppm
FSR/
o
C
ppm
FSR/
o
C
Full Scale Gain Drifta
With External Reference (Note 7)
With Internal Reference (Note 7)
Gain Matching Between Channels
I/Q Channel Isolation
Output Voltage Compliance Range
Full Scale Output Current, I
FS
DYNAMIC CHARACTERISTICS
(Per Channel)
Clock Rate, f
CLK
Output Settling Time, (t
SETT
)
Singlet Glitch Area (Peak Glitch)
Output Rise Time
Output Fall Time
Output Capacitance
Output Noise
IOUTFS = 20mA
IOUTFS = 2mA
(Note 3, 9)
0.8% (1 LSB, equivalent to 7 Bits) (Note 7)
0.4% (1/2 LSB, equivalent to 8 Bits) (Note 7)
R
L
= 25(Note 7)
Full Scale Step
Full Scale Step
F
OUT
= 10MHz
(Note 3)
dB
dB
V
mA
-
-0.3
2
125
-
-
-
-
-
-
-
-
-
5
15
5
1.5
1.5
10
50
30
-
-
-
-
-
-
-
-
-
MHz
ns
ns
pV•s
ns
ns
pF
pA/Hz
pA/Hz
FN4520 Rev 5.00
September 2000
Page 4 of 10
HI5628
Electrical Specifications
AV
DD
= +5V, DV
DD
= +5V, V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25
o
C for All Typical Values. Data
given is per channel except for ‘Power Supply Characteristics.’
(Continued)
HI5628IN
T
A
= -40
o
C TO 85
o
C
PARAMETER
AC CHARACTERISTICS - HI5628IN - 125MHz
(Per Channel)
Spurious Free Dynamic Range,
SFDR Within a Window
f
CLK
= 125MSPS, f
OUT
= 32.9MHz, 10MHz Span (Notes 4, 7)
f
CLK
= 100MSPS, f
OUT
= 5.04MHz, 4MHz Span (Notes 4, 7)
f
CLK
= 125MSPS, f
OUT
= 32.9MHz, 62.5MHz Span (Notes 4, 7)
f
CLK
= 125MSPS, f
OUT
= 10.1MHz, 62.5MHz Span (Notes 4, 7)
f
CLK
= 100MSPS, f
OUT
= 40.4MHz, 50MHz Span (Notes 4, 7)
f
CLK
= 100MSPS, f
OUT
= 20.2MHz, 50MHz Span (Notes 4, 7)
f
CLK
= 100MSPS, f
OUT
= 5.04MHz, 50MHz Span (Notes 4, 7)
f
CLK
= 100MSPS, f
OUT
= 2.51MHz, 50MHz Span (Notes 4, 7)
AC CHARACTERISTICS - HI5628/6IN - 60MHz
(Per Channel)
Spurious Free Dynamic Range,
SFDR Within a Window
f
CLK
= 60MSPS, f
OUT
= 10.1MHz, 10MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, 2MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 1.00MHz, 2MHz Span (Notes 4, 7)
Total Harmonic Distortion (THD) to Nyquist f
CLK
= 50MSPS, f
OUT
= 2.00MHz (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 1.00MHz (Notes 4, 7)
Spurious Free Dynamic Range,
SFDR to Nyquist
f
CLK
= 60MSPS, f
OUT
= 20.2MHz, 30MHz Span (Notes 4, 7)
f
CLK
= 60MSPS, f
OUT
= 10.1MHz, 30MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 20.2MHz, 25MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, 25MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 2.51MHz, 25MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 1.00MHz, 25MHz Span (Notes 4, 7)
f
CLK
= 25MSPS, f
OUT
= 5.02MHz, 25MHz Span (Notes 4, 7)
VOLTAGE REFERENCE
Internal Reference Voltage, V
FSADJ
Internal Reference Voltage Drift
Internal Reference Output Current
Sink/Source Capability
Reference Input Impedance
Reference Input Multiplying Bandwidth
DIGITAL INPUTS
(Note 7)
Voltage at Pin 22 with Internal Reference
1.04
-
-
-
-
1.16
60
0.1
1
1.4
1.28
-
-
-
-
V
ppm
/
o
C
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
-
-
-
-
-
-
-
-
70
73
67
51
61
48
56
68
68
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Total Harmonic Distortion (THD) to Nyquist f
CLK
= 100MSPS, f
OUT
= 2.00MHz (Notes 4, 7)
Spurious Free Dynamic Range,
SFDR to Nyquist
-
-
-
-
-
-
-
-
-
-
-
-
70
73
74
67
68
54
60
53
67
68
68
71
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
A
M
MHz
D7-D0, CLK (Per Channel)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
3.5
2.1
-
-
-10
-10
-
5
3
0
0
-
-
5
-
-
1.3
0.9
+10
+10
-
V
V
V
V
A
A
pF
Input Logic High Voltage with
5V Supply, V
IH
Input Logic High Voltage with
3V Supply, V
IH
Input Logic Low Voltage with
5V Supply, V
IL
Input Logic Low Voltage with
3V Supply, V
IL
Input Logic Current, I
IH
Input Logic Current, I
IL
Digital Input Capacitance, C
IN
FN4520 Rev 5.00
September 2000
Page 5 of 10
stm32/stm8
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