74VCX162240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26:
Series Resistors in Outputs
January 1998
Revised June 2005
74VCX162240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
and 26: Series Resistors in Outputs
General Description
The VCX162240 contains sixteen inverting buffers with
3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The 74VCX162240 is designed for low voltage (1.4V to
3.6V) V
CC
applications with I/O capability up to 3.6V. The
74VCX162240 is also designed with 26
:
series resistors in
the outputs. This design reduces line noise in applications
such as memory address drivers, clock drivers, and bus
transceivers/transmitters.
The 74VCX162240 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
1.4V to 3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
26
:
series resistors in outputs
s
t
PD
3.3 ns max for 3.0V to 3.6V V
CC
s
Power-off high impedance inputs and outputs
s
Supports live insertion and withdrawal (Note 1)
s
Static Drive (I
OH
/I
OL
)
r
12 mA @ 3.0V V
CC
s
Uses patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 300 mA
s
ESD performance:
Human body model
!
2000V
Machine model
!
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
74VCX162240MTD
Package Number
MTD48
Package Descriptions
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
n
I
0
–I
15
O
0
–O
15
Description
Output Enable Input (Active LOW)
Inputs
Outputs
© 2005 Fairchild Semiconductor Corporation
DS500091
www.fairchildsemi.com
74VCX162240
Connection Diagram
Truth Tables
Inputs
OE
1
L
L
H
Inputs
OE
2
L
L
H
Inputs
OE
3
L
L
H
Inputs
OE
4
L
L
H
I
12
–I
15
L
H
X
I
8
–I
11
L
H
X
I
4
–I
7
L
H
X
I
0
–I
3
L
H
X
Outputs
O
0
–O
3
H
L
Z
Outputs
O
4
–O
7
H
L
Z
Outputs
O
8
–O
11
H
L
Z
Outputs
O
12
–O
15
H
L
Z
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial (HIGH or LOW, inputs may not float)
Z High Impedance
Functional Description
The 74VCX162240 contains sixteen inverting buffers with
3-STATE outputs. The device is nibble (4 bits) controlled
with each nibble functioning identically, but independent of
each other. The control pins may be shorted together to
obtain full 16-bit operation.The 3-STATE outputs are con-
trolled by an Output Enable (OE
n
) input. When OE
n
is
LOW, the outputs are in the 2-state mode. When OE
n
is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the inputs.
Logic Diagram
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2
74VCX162240
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
Output Voltage (V
O
)
Outputs 3-STATED
Outputs Active (Note 3)
DC Input Diode Current (I
IK
) V
I
0V
DC Output Diode Current (I
OK
)
V
O
0V
V
O
!
V
CC
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
Storage Temperature Range (T
STG
)
0.5V to
4.6V
0.5V to
4.6V
0.5V to
4.6V
0.5V to V
CC
0.5V
50.0 mA
50.0 mA
50.0 mA
r
50.0 mA
r
100 mA
65
q
C to
150
q
C
Recommended Operating
Conditions
(Note 4)
Power Supply
Operating
Data Retention Only
Input Voltage
Output Voltage (V
O
)
Output in Active States
Output in 3-State
Output Current in I
OH
/I
OL
V
CC
V
CC
V
CC
V
CC
3.0V to 3.6V
2.3V to 2.7V
1.65V to 2.3V
1.4V to 1.6V
0V to V
CC
0.0V to 3.6V
1.4V to 3.6V
1.2V to 3.6V
0.3V to
3.6V
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (
'
t/
'
V)
V
IN
0.8V to 2.0V, V
CC
3.0V
r
12.0 mA
r
8.0 mA
r
3.0 mA
r
2.0 mA
40
q
C to
85
q
C
10.0 ns/V
Note 2:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 3:
I
O
Absolute Maximum Rating must be observed.
Note 4:
Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level Input Voltage
Conditions
V
CC
(V)
2.7
3.6
2.3
2.7
1.65 - 2.3
1.4 - 1.6
V
IL
LOW Level Input Voltage
2.7
3.6
2.3
2.7
1.65 - 2.3
1.4 - 1.6
V
OH
HIGH Level Output Voltage
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
2.0
1.6
0.65
u
V
CC
0.65
u
V
CC
0.8
0.7
0.35
u
V
CC
0.35
u
V
CC
V
CC
0.2
2.2
2.4
2.2
V
CC
0.2
2.0
1.8
1.7
V
CC
0.2
1.25
V
CC
0.2
1.05
V
V
V
Min
Max
Units
100
P
A
6 mA
8 mA
12 mA
100
P
A
4 mA
6 mA
8 mA
100
P
A
3 mA
100
P
A
1 mA
2.7
3.6
2.7
3.0
3.0
2.3
2.7
2.3
2.3
2.3
1.65 - 2.3
1.65
1.4 - 1.6
1.4
3
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74VCX162240
DC Electrical Characteristics
Symbol
V
OL
Parameter
LOW Level Output Voltage
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
I
I
OZ
I
OFF
I
CC
Input Leakage Current
3-STATE Output Leakage
Power-OFF Leakage Current
Quiescent Supply Current
Increase in I
CC
per Input
(Continued)
V
CC
(V)
100
P
A
6 mA
8 mA
12 mA
100
P
A
6 mA
8 mA
100
P
A
3 mA
100
P
A
1 mA
2.7
3.6
2.7
3.0
3.0
2.3
2.7
2.3
2.3
1.65 - 2.3
1.65
1.4 - 1.6
1.4
1.4 - 3.6
1.4 - 3.6
0
1.4 - 3.6
1.4 - 3.6
2.7 - 3.6
0.2
0.4
0.55
0.80
0.2
0.4
0.6
0.2
0.3
0.2
0.35
V
Conditions
Min
Max
Units
0
d
V
I
d
3.6V
0
d
V
O
d
3.6V
V
I
V
I
V
IH
V
IH
or V
IL
V
CC
or GND
V
CC
0.6V
0
d
(V
I
, V
O
)
d
3.6V
V
CC
d
(V
I
, V
O
)
d
3.6V (Note 5)
r
5.0
r
10.0
10.0
20.0
P
A
P
A
P
A
P
A
P
A
r
20.0
750
'
I
CC
Note 5:
Outputs disabled or 3-STATE only.
AC Electrical Characteristics
(Note 6)
Symbol
t
PHL
,
t
PLH
C
L
t
PZL
,
t
PZH
C
L
t
PLZ
, t
PHZ
Output Disable Time
C
L
15 pF, R
L
30 pF, R
L
2k
:
500
:
Output Enable Time
C
L
15 pF, R
L
30 pF, R
L
2k
:
500
:
Parameter
Propagation Delay
C
L
Conditions
30 pF, R
L
500
:
V
CC
(V)
3.3
r
0.3
2.5
r
0.2
1.8
r
0.15
1.5
r
0.1
3.3
r
0.3
2.5
r
0.2
1.8
r
0.15
1.5
r
0.1
3.3
r
0.3
2.5
r
0.2
1.8
r
0.15
C
L
t
OSHL
t
OSLH
Output to Output Skew
(Note 7)
C
L
Note 6:
For C
L
T
A
40
q
C to
85
q
C
Max
3.3
3.8
7.6
15.2
3.8
5.1
9.8
19.6
3.6
4.0
7.2
14.4
0.5
0.5
0.75
1.5
Units
Figure
Number
Figures 1,
2
Figures 5,
6
Figures 1,
3, 4
Figures 5,
7, 8
Figures 1,
3, 4
Figures 5,
7, 8
Min
0.8
1.0
1.5
1.0
0.8
1.0
1.5
1.0
0.8
1.0
1.5
1.0
ns
ns
ns
15 pF, R
L
30 pF, R
L
2k
:
500
:
1.5
r
0.1
3.3
r
0.3
2.5
r
0.2
1.8
r
0.15
C
L
ns
15 pF, R
L
2k
:
1.5
r
0.1
50
P
F, add approximately 300 ps to the AC maximum specification.
Note 7:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
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4
74VCX162240
Dynamic Switching Characteristics
Symbol
V
OLP
Parameter
Quiet Output Dynamic Peak V
OL
C
L
30 pF, V
IH
Conditions
V
CC
, V
IL
0V
V
CC
(V)
1.8
2.5
3.3
V
OLV
Quiet Output Dynamic Valley V
OL
C
L
30 pF, V
IH
V
CC
, V
IL
0V
1.8
2.5
3.3
V
OHV
Quiet Output Dynamic Valley V
OH
C
L
30 pF, V
IH
V
CC
, V
IL
0V
1.8
2.5
3.3
T
A
25
q
C
0.15
0.25
0.35
Typical
Units
V
0.15
0.25
0.35
1.55
2.05
2.65
V
V
Capacitance
Symbol
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Parameter
V
CC
V
I
V
I
Conditions
1.8, 2.5V or 3.3V, V
I
0V or V
CC
, V
CC
0V or V
CC
, f
0V or V
CC
1.8V, 2.5V or 3.3V
T
A
25
q
C
6.0
7.0
20.0
Typical
Units
pF
pF
pF
1.8V, 2.5V or 3.3V
10 MHz, V
CC
5
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