HI5746
10-Bit, 40MSPS A/D Converter
S I GN S
NE W D E
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DATASHEET
FN4129
Rev 5.00
July 2004
The HI5746 is a monolithic, 10-bit, analog-to-digital
converter fabricated in a CMOS process. It is designed for
high speed applications where wide bandwidth and low
power consumption are essential. Its 40MSPS speed is
made possible by a fully differential pipelined architecture
with an internal sample and hold.
The HI5746 has excellent dynamic performance while
consuming only 225mW power at 40MSPS. Data output
latches are provided which present valid data to the output
bus with a latency of 7 clock cycles. It is pin-for-pin
functionally compatible with the HI5702 and the HI5703.
For internal voltage reference, please refer to the HI5767
data sheet.
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 40MSPS
• 8.8 Bits at f
IN
= 10MHz
• Low Power at 40MSPS . . . . . . . . . . . . . . . . . . . . 225mW
• Wide Full Power Input Bandwidth . . . . . . . . . . . . 250MHz
• On-Chip Sample and Hold
• Fully Differential or Single-Ended Analog Input
• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . +5V
• TTL/CMOS Compatible Digital Inputs
• CMOS Compatible Digital Outputs. . . . . . . . . . . . 3.0/5.0V
• Offset Binary or Two’s Complement Output Format
•
Pb-free Available
Ordering Information
PART
NUMBER
HI5746KCB
HI5746KCBZ
(Note)
HI5746KCBZ-T
(Note)
HI5746KCA
HI5746KCAZ
(Note)
HI5746EVAL1
TEMP.
RANGE (°C)
0 to 70
0 to 70
PACKAGE
28 Ld SOIC (W)
28 Ld SOIC (W)
(Pb-free)
PKG.
DWG. #
M28.3
M28.3
M28.3
M28.15
M28.15
Applications
• Professional Video Digitizing
• Medical Imaging
• Digital Communication Systems
• High Speed Data Acquisition
28 Ld SOIC (W) Tape and Reel
(Pb-free)
0 to 70
0 to 70
25
28 Ld SSOP
28 Ld SSOP
(Pb-free)
Evaluation Board
Pinout
HI5746
(SOIC, SSOP)
TOP VIEW
DV
CC1
1
DGND1 2
DV
CC1
3
DGND1 4
AV
CC
5
AGND 6
V
REF
+ 7
V
REF
- 8
V
IN
+ 9
V
IN
- 10
V
DC
11
AGND 12
AV
CC
13
OE 14
28 D0
27 D1
26 D2
25 D3
24 D4
23 DV
CC2
22 CLK
21 DGND2
20 D5
19 D6
18 D7
17 D8
16 D9
15 DFS
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
FN4129 Rev 5.00
July 2004
Page 1 of 16
HI5746
Functional Block Diagram
V
DC
V
IN
-
V
IN
+
S/H
BIAS
CLOCK
CLK
STAGE 1
DFS
2-BIT
FLASH
2-BIT
DAC
OE
+
-
DV
CC2
X2
D9 (MSB)
D8
D7
D6
STAGE 8
DIGITAL DELAY
AND
DIGITAL ERROR
CORRECTION
D5
D4
D3
2-BIT
FLASH
2-BIT
DAC
D2
D1
+
D0 (LSB)
-
X2
DGND2
STAGE 9
2-BIT
FLASH
AV
CC
AGND
DV
CC1
DGND1
V
REF
+
V
REF
- (OPTIONAL)
FN4129 Rev 5.00
July 2004
Page 2 of 16
HI5746
Typical Application Schematic
HI5746
2.5V
2.0V
(OPTIONAL)
V
REF
+ (7)
V
REF
- (8)
(LSB) (28) D0
(27) D1
AGND (12)
AGND (6)
DGND1 (2)
DGND1 (4)
DGND2 (21)
(26) D2
(25) D3
(24) D4
(20) D5
(19) D6
(18) D7
(17) D8
(MSB) (16) D9
V
IN
+
V
IN
+ (9)
V
DC
(11)
V
IN
-
V
IN
- (10)
(1) DV
CC1
(3) DV
CC1
(23) DV
CC2
0.1F
CLOCK
CLK (22)
DFS (15)
OE (14)
(13) AV
CC
(5) AV
CC
0.1F
+
10F
+5V
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
10F AND 0.1F CAPS
ARE PLACED AS CLOSE
TO PART AS POSSIBLE
+
10F
+5V
DGND
AGND
BNC
Pin Descriptions
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NAME
DV
CC1
DGND1
DV
CC1
DGND1
AV
CC
AGND
V
REF
+
V
REF
-
V
IN
+
V
IN
-
V
DC
AGND
AV
CC
OE
DFS
DESCRIPTION
Digital Supply (+5.0V).
Digital Ground.
Digital Supply (+5.0V).
Digital Ground.
Analog Supply (+5.0V).
Analog Ground.
+2.5V Positive Reference Voltage
Input.
+2.0V Negative Reference Voltage
Input (Optional).
Positive Analog Input.
Negative Analog Input.
DC Bias Voltage Output.
Analog Ground.
Analog Supply (+5.0V).
Digital Output Enable Control Input.
Data Format Select Input.
PIN NO.
16
17
18
19
20
21
22
23
24
25
26
27
28
NAME
D9
D8
D7
D6
D5
DGND2
CLK
DV
CC2
D4
D3
D2
D1
D0
DESCRIPTION
Data Bit 9 Output (MSB).
Data Bit 8 Output.
Data Bit 7 Output.
Data Bit 6 Output.
Data Bit 5 Output.
Digital Ground.
Sample Clock Input.
Digital Output Supply
(+3.0V or +5.0V).
Data Bit 4 Output.
Data Bit 3 Output.
Data Bit 2 Output.
Data Bit 1 Output.
Data Bit 0 Output (LSB).
FN4129 Rev 5.00
July 2004
Page 3 of 16
HI5746
Absolute Maximum Ratings
T
A
= 25
o
C
Supply Voltage, AV
CC
or DV
CC
to AGND or DGND . . . . . . . . . . .6V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DV
CC
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AV
CC
Thermal Information
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
Operating Conditions
Temperature Range
HI5746KCB (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . .
-
65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC, SSOP - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AV
CC
= DV
CC1
= 5.0V; DV
CC2
= 3.0V, V
REF
+ = 2.5V; V
REF
- = 2.0V; f
S
= 40 MSPS at 50% Duty Cycle;
C
L
= 10pF; T
A
= 25
o
C; Differential Analog Input; Typical Values are Test Results at 25
o
C,
Unless Otherwise Specified
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
ACCURACY
Resolution
Integral Linearity Error, INL
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
Offset Error, V
OS
Full Scale Error, FSE
DYNAMIC CHARACTERISTICS
Minimum Conversion Rate
Maximum Conversion Rate
Effective Number of Bits, ENOB
Signal to Noise and Distortion Ratio, SINAD
RMS Signal
-
= -------------------------------------------------------------
RMS Noise + Distortion
Signal to Noise Ratio, SNR
RMS Signal
-
= ------------------------------
RMS Noise
Total Harmonic Distortion, THD
2nd Harmonic Distortion
3rd Harmonic Distortion
Spurious Free Dynamic Range, SFDR
Intermodulation Distortion, IMD
Differential Gain Error
Differential Phase Error
Transient Response
Over-Voltage Recovery
f
IN
= DC
f
IN
= DC
f
IN
= DC
f
IN
= DC
10
-
-
-40
-
-
1.0
0.5
12
4
-
2.0
1.0
40
-
Bits
LSB
LSB
LSB
LSB
No Missing Codes
No Missing Codes
f
IN
= 10MHz
f
IN
= 10MHz
-
40
8.55
53.2
0.5
-
8.8
54.9
1
-
-
-
MSPS
MSPS
Bits
dB
f
IN
= 10MHz
53.2
55.4
-
dB
f
IN
= 10MHz
f
IN
= 10MHz
f
IN
= 10MHz
f
IN
= 10MHz
f
1
= 1MHz, f
2
= 1.02MHz
f
S
= 17.72 MSPS, 6 Step, Mod Ramp
f
S
= 17.72 MSPS, 6 Step, Mod Ramp
(Note 2)
0.2V Overdrive (Note 2)
-
-
-
-
-
-
-
-
-
-64.6
-67.8
-68.3
67.8
64
0.8
0.1
1
1
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
%
Degree
Cycle
Cycle
FN4129 Rev 5.00
July 2004
Page 4 of 16
HI5746
Electrical Specifications
AV
CC
= DV
CC1
= 5.0V; DV
CC2
= 3.0V, V
REF
+ = 2.5V; V
REF
- = 2.0V; f
S
= 40 MSPS at 50% Duty Cycle;
C
L
= 10pF; T
A
= 25
o
C; Differential Analog Input; Typical Values are Test Results at 25
o
C,
Unless Otherwise Specified
(Continued)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
ANALOG INPUT
Maximum Peak-to-Peak Differential Analog Input
Range (V
IN
+ - V
IN
-)
Maximum Peak-to-Peak Single-Ended
Analog Input Range
Analog Input Resistance, R
IN
Analog Input Capacitance, C
IN
Analog Input Bias Current, I
B
+ or I
B
-
Differential Analog Input Bias Current
I
BDIFF
= (I
B
+ - I
B
-)
Full Power Input Bandwidth, FPBW
Analog Input Common Mode Voltage Range
(V
IN
+ + V
IN
-)/2
REFERENCE INPUT
Total Reference Resistance, R
L
Positive Reference Current, I
REF
+
Negative Reference Current, I
REF
-
Positive Reference Voltage Input, V
REF
+
Negative Reference Voltage Input, V
REF
-
Reference Common Mode Voltage
(V
REF
+ + V
REF
-)/2
DC BIAS VOLTAGE
DC Bias Voltage Output, V
DC
Maximum Output Current
DIGITAL INPUTS
Input Logic High Voltage, V
IH
Input Logic Low Voltage, V
IL
Input Logic High Current, I
IH
Input Logic Low Current, I
IL
Input Capacitance, C
IN
DIGITAL OUTPUTS
Output Logic High Voltage, V
OH
Output Logic Low Voltage, V
OL
Output Three-State Leakage Current, I
OZ
Output Logic High Voltage, V
OH
Output Logic Low Voltage, V
OL
(Note 2)
(Note 2)
(Note 2)
(Note 3)
(Note 3)
(Note 3)
-
-
-
-
-10
-
-
Differential Mode (Note 2)
0.25
0.5
1.0
1
10
-
0.5
250
-
-
-
-
-
+10
-
-
4.75
V
V
M
pF
A
A
MHz
V
V
REF
+ to AGND
-
-
-
-
-
-
2.5K
1.07
21
2.5
2.0
2.25
-
-
-
-
-
-
mA
A
V
V
V
-
-
3.2
-
-
0.4
V
mA
CLK, DFS, OE
CLK, DFS, OE
CLK, DFS, OE, V
IH
= 5V
CLK, DFS, OE, V
IL
= 0V
2.0
-
-10.0
-10.0
-
-
-
-
-
7
-
0.8
+10.0
+10.0
-
V
V
A
A
pF
I
OH
= 100A; DV
CC2
= 5V
I
OL
= 100A; DV
CC2
= 5V
V
O
= 0/5V; DV
CC2
= 5V
I
OH
= 100A; DV
CC2
= 3V
I
OL
= 100A; DV
CC2
= 3V
4.0
-
-
2.4
-
-
-
1
-
-
-
0.5
10
-
0.5
V
V
A
V
V
FN4129 Rev 5.00
July 2004
Page 5 of 16
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