November 2002
DU CT
UC T
E P RO
P RO D t
ET
L
TE
O BS O
STITU
er a
E S UB u p p o r t Ce n t s c
I BL
POSS
al S
om / t
FOR A our Technic ww.intersil.c
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contac TERSIL or w
IN
1-888-
®
HI3304
4-Bit, 25 MSPS, Flash A/D Converter
Features
• CMOS Low Power (Typ) . . . . . . . . . . . . . . . . . . . 35mW
• Parallel Conversion Technique
• Single Power Supply Voltage . . . . . . . . . . . . 3V to 7.5V
• Sampling Rate at 5V Supply . . . . . . . . . . . . . . . . . 25MHz
• 4-Bit Latched Three-State Output with Overflow and
Data Change Outputs
• Maximum Nonlinearity. . . . . . . . . . . . . . . . . . . .
1
/
8
LSB
• Inherent Resistance to Latch-Up
• Bipolar Input Range with Optional Second Supply
• Input Bandwidth (Typ) . . . . . . . . . . . . . . . . . . . . . 40MHz
• Linearity (INL, DNL):
- HI3304JIP . . . . . . . . . . . . . . . . . . . . . . . . . .
±0.25
LSB
- HI3304JIB . . . . . . . . . . . . . . . . . . . . . . . . . .
±0.25
LSB
• Sampling Rate:
- HI3304JIP . . . . . . . . . . . . . . . . . . . . . . . .25MHz (40ns)
- HI3304JIB . . . . . . . . . . . . . . . . . . . . . . . .25MHz (40ns)
Description
The Intersil HI3304 is a CMOS parallel (FLASH) analog-to-
digital converter designed for applications demanding both
low-power consumption and high speed digitization. Digitiz-
ing at 25MHz, for example, requires only about 35mW.
The HI3304 operates over a wide, full-scale signal input volt-
age range of 0.5V up to the supply voltage. Power consump-
tion is as low as 10mW, depending upon the clock frequency
selected.
Sixteen paralleled auto-balanced voltage comparators mea-
sure the input voltage with respect to a known reference to
produce the parallel-bit outputs in the HI3304. Fifteen com-
parators are required to quantize all input voltage levels in
this 4-bit converter, and the additional comparator is
required for the overflow bit. A data change pin indicates
when the present output differs from the previous, thus
allowing compaction of data storage.
Part Number Information
PART NUMBER
TEMP.
RANGE (
o
C)
-40 to 85
-40 to 85
PACKAGE
16 Ld PDIP
16 Ld SOIC
PKG. NO.
E16.3
M16.3
Applications
• Video Digitizing
• High Speed Data Acquisition
• Digital Communication Systems
• Radar Signal Processing
HI3304JIP
HI3304JIB
Pinout
HI3304
(PDIP, SOIC)
TOP VIEW
BIT 1 (LSB) 1
BIT 2 2
BIT 3 3
BIT 4 4
DATA CHANGE (DC) 5
OVERFLOW (OF) 6
CE2 7
V
SS
8
16 V
DD
15 CLK
14 V
AA
-
13 V
REF
-
12 V
REF
+
11 V
IN
10 V
AA
+
9 CE1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
FN4137.2
1
HI3304
Functional Block Diagram
φ
2
V
AA
+
V
DD
16
OUTPUT
REGISTER
D Q
CLK
THREE-STATE
DRIVERS
5 DATA
CHANGE
φ
2
φ
1
V
IN
11
1
/ R
2
φ
1
φ
1
φ
1
10
D
COUNT
16
Q
D Q
CLK
6 OVERFLOW
12
V
REF
+
R
†
CAB #16
LATCH
16
D Q
CLK
COUNT
ENCODER
8
LOGIC
Q
D
ARRAY
LATCH
8
4 BIT 4
R
†CAB
#8
R
D Q
CLK
3 BIT 3
D Q
CLK
2 BIT 2
R
V
REF
-
1
13
50kΩ
CLOCK
15
/
2
R
D
COUNT
1
Q
†
CAB COMPARATOR #1
φ
1 (AUTO BALANCE)
LATCH
0
14
V
AA
-
8
V
SS
D Q
CLK
1 BIT 1 (LSB)
9 CE1
φ
2 (SAMPLE UNKNOWN)
7 CE2
†
Cascaded Auto Balance (CAB)
NOTE: CE1 and CE2 inputs and data outputs have standard CMOS protection networks to V
DD
and V
SS
. Analog inputs and clock have
standard CMOS protection networks to V
AA
+ and V
AA
-.
2
HI3304
Absolute Maximum Ratings
DC Supply Voltage Range (V
DD
or V
AA
+)
(Voltage Referenced to V
SS
or V
AA
- Terminal,
Whichever is More Negative) . . . . . . . . . . . . . . . . . . -0.5V to +8V
Input Voltage Range
CE1, CE2 Inputs . . . . . . . . . . . . . . . . . . . V
SS
-0.5V to V
DD
+0.5V
Clock, V
REF
+, V
REF
-, V
IN
Inputs . . . . . . V
AA
-0.5V to V
AA
+0.5V
DC Input Current, Any Input . . . . . . . . . . . . . . . . . . . . . . . . .
±20mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range (T
STG
) . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Supply Voltage Range (V
DD
or V
AA
+). . . . . . . . . . . . . . . . . . 3V to 7.5V
V
AA
+ Voltage Range . . . . . . . . . . . . . . . . . . V
DD
-1V to V
DD
+2.5V
V
AA
- Voltage Range. . . . . . . . . . . . . . . . . . . . V
SS
-2.5V to V
SS
+1V
Operating Temperature Range. . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
T
A
= 25
o
C, V
REF
+ = 2V, V
DD
= V
AA
+ = 5V, V
AA
- = V
REF
- = V
SS
= GND, f
CLK
= 25MHz
Unless Otherwise Specified
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
SYSTEM PERFORMANCE
Resolution
Input Errors
Integral Linearity Error
Differential Linearity Error
Offset Error (Unadjusted)
Gain Error (Unadjusted)
4
-
-
-
-
-
±0.125
±0.125
-
-
-
±0.25
±0.25
±1.0
±1.0
Bits
LSB
LSB
LSB
LSB
DYNAMIC CHARACTERISTICS
Input Signal Level 0.5dB Below Full Scale
Conversion Timing
Aperture Delay
f
S
= 25MHz, f
IN
= 100kHz
f
S
= 25MHz, f
IN
= 5MHz
f
S
= 25MHz, f
IN
= 100kHz
f
S
= 25MHz, f
IN
= 5MHz
f
S
= 25MHz, f
IN
= 100kHz
f
S
= 25MHz, f
IN
= 5MHz
Effective Number of Bits, ENOB
f
S
= 25MHz, f
IN
= 100kHz
f
S
= 25MHz, f
IN
= 5MHz
ANALOG INPUTS
Input Range
Input Loading
Full Scale Input Range
Input Capacitance
Input Current
-3dB Input Bandwidth
V
IN
= 2V (Note 2)
(Notes 1, 4)
0.5
-
-
-
-
10
150
40
V
AA
-
200
-
V
pF
µA
MHz
-
-
-
3
23.7
23.6
-
-
-
ns
dB
dB
Signal to Noise Ratio (SNR)
RMS Signal
=
----------------------------------
RMS Noise
Signal to Noise Ratio (SINAD)
RMS Signal
-
=
---------------------------------------------------------------
RMSNoise + Distortion
Total Harmonic Distortion, THD
-
-
23.4
22.8
-
-
dB
dB
-
-
-
-
-34.5
-31.0
3.67
3.57
-
-
-
-
dBc
dBc
Bits
Bits
3
HI3304
Electrical Specifications
T
A
= 25
o
C, V
REF
+ = 2V, V
DD
= V
AA
+ = 5V, V
AA
- = V
REF
- = V
SS
= GND, f
CLK
= 25MHz
Unless Otherwise Specified
(Continued)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
REFERENCE INPUTS
Input Range
V
REF
+ Range
V
REF
- Range
Input Loading
DIGITAL INPUTS
Digital Input
Maximum V
IN
, Low
CLOCK
CE1, CE2
Minimum V
IN
, High
CLOCK
CE1, CE2
Input Leakage, Except CLK
Input Leakage, CLK
DIGITAL OUTPUTS
Digital Outputs
Output Low (Sink) Current
Output High (Source) Current
Three-State Leakage Current
TIMING CHARACTERISTICS
Conversion Timing
Maximum Conversion Speed
Auto-Balance Time (
φ
1)
Sample Time (
φ
2)
Output Timing
Data Valid Delay
Data Hold Time
Output Enable Time
Output Disable Time
POWER SUPPLY CHARACTERISTICS
Device Current, I
AA
Resistor Ladder Impedance
(Note 4)
(Note 4)
V
IN
= 5V, CLK = Low
V
AA
- +0.5
V
AA
-
640
-
-
-
V
AA
+
V
AA
+ -0.5
960
V
V
Ω
(Notes 3, 4)
(Note 4)
(Notes 3, 4)
(Note 4)
V = 0V, 5V
(Note 3)
-
-
0.7 x V
AA
0.7 x V
DD
-
-
-
-
-
-
-
±100
0.3 x V
AA
0.3 x V
DD
-
-
±1
±150
V
V
V
V
µA
µA
V
O
= 0.4V
V
O
= 4.6V
V
O
= 0V, 5V
6
-3
-
-
-
±0.2
-
-
±5
mA
mA
µA
CLK = Square Wave
25
20
20
35
-
-
30
25
15
10
-
MSPS
ns
ns
ns
ns
ns
ns
-
5000
40
-
-
-
(Note 4)
(Note 4)
-
15
-
-
Continuous Clock
Continuous
φ
2
Continuous
φ
1
-
-
-
-
-
5.5
0.4
2
1.5
5
-
-
-
-
10
mA
mA
mA
mA
mA
Device Current, I
DD
V
AA
+ = 5V,
V
SS
= CE1 = V
AA
- = CLK = GND
V
AA
+ = 7V
NOTES:
Continuous Clock
Continuous
φ
2
Continuous
φ
1
-
5
20
mA
1. Full scale input range, V
REF
+ - V
REF
-, may be in the range of 0.5V to V
AA
+ -V
AA
- volts. Linearity errors increase at lower full scale ranges,
however.
2. Input current is due to energy transferred to the input at the start of the sample period. The average value is dependent on input and VDD
voltage.
3. The CLK input is a CMOS inverter with a 50kΩ feedback resistor. It operates from the V
AA
+ and V
AA
- supplies. It may be AC-coupled
with a 1V
P-P
minimum source.
4. Parameter not tested, but guaranteed by design or characterization.
4
HI3304
Timing Diagrams
DATA SHIFTED INTO
OUTPUT REGISTERS
COMPARATOR DATA
LATCHED
1
CLOCK
0
1
B1 - B4, DC AND OF
0
φ
1
AUTO
BALANCE
φ
2
SAMPLE 1
AUTO
BALANCE
SAMPLE 2
AUTO
BALANCE
SAMPLE 3
DATA VALID 0
t
HO
t
D
DATA VALID 1
DATA VALID 2
FIGURE 1. TIMING DIAGRAM
CE1
CE2
t
DIS
BITS 1-4
HIGH
IMPEDANCE
t
EN
t
DIS
t
EN
HIGH
IMPEDANCE
HIGH
IMPEDANCE
DC, OF
FIGURE 2. OUTPUT ENABLE/DISABLE TIMING
SAMPLE ENDS
CLOCK
SAMPLE ENDS
φ
2
OLD DATA
φ
1
t
D
φ
2
NEW DATA
CLOCK
φ
1
φ
2
φ
1
t
D
φ
2
φ
1
NEW DATA
OUTPUT
OUTPUT
OLD DATA
OLD DATA + 1
FIGURE 3A.
With
φ
2 as standby state (fastest method, but standby limited to 5µs
maximum)
FIGURE 3B.
With
φ
1 as standby state (indefinite standby, double pulse needed)
SAMPLE ENDS
CLOCK
φ
2
φ
1
OLD DATA
φ
2
φ
1
t
D
φ
2
NEW DATA
OUTPUT
INVALID DATA
FIGURE 3C.
With
φ
2 as standby state (indefinite standby, lower power than 3B)
FIGURE 3. PULSE-MODE TIMING DIAGRAMS
5
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