CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
V
DD
= V
AA
+ = 5V, V
REF
+ = +4.608V, V
SS
= V
AA
- = V
REF
- = GND, CLK = External 750kHz,
Unless Otherwise Specified
25
o
C
-
40
o
C TO 85
o
C
MAX
MIN
MAX
UNITS
PARAMETER
ACCURACY
Resolution
Integral Linearity Error, INL
(End Point)
Differential Linearity Error, DNL
J
K
J
K
Gain Error, FSE
(Adjustable to Zero)
Offset Error, V
OS
(Adjustable to Zero)
Power Supply Rejection, PSRR
Offset Error PSRR
Gain Error PSRR
DYNAMIC CHARACTERISTICS
Signal to Noise Ratio, SINAD
RMS Signal
RMS Noise + Distortion
Signal to Noise Ratio, SNR
RMS Signal
RMS Noise
Total Harmonic Distortion, THD
J
K
J
K
J
K
J
K
J
K
TEST CONDITIONS
MIN
TYP
12
-
-
-
-
-
-
-
-
V
REF
= 4V
V
DD
½V
AA
+ = 5V
5%
V
DD
½V
AA
+ = 5V
5%
-
-
-
-
-
-
-
-
-
-
±0.1
±0.1
-
1.5
1.0
2.0
1.0
3.0
2.5
2.0
1.0
0.5
0.5
12
-
-
-
-
-
-
-
-
-
-
1.5
1.0
2.0
1.0
3.0
2.5
2.0
1.0
0.5
0.5
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 750kHz, f
IN
= 1kHz
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 750kHz, f
IN
= 1kHz
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 750kHz, f
IN
= 1kHz
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 750kHz, f
IN
= 1kHz
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 750kHz, f
IN
= 1kHz
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 750kHz, f
IN
= 1kHz
-
-
-
-
-
-
68.8
69.2
71.0
71.5
70.5
71.1
71.5
72.1
-73.9
-73.8
-80.3
-79.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dBc
dBc
dBc
dBc
FN3214 Rev 6.00
March 31, 2005
Page 3 of 16
HI5812
Electrical Specifications
V
DD
= V
AA
+ = 5V, V
REF
+ = +4.608V, V
SS
= V
AA
- = V
REF
- = GND, CLK = External 750kHz,
Unless Otherwise Specified
(Continued)
25
o
C
PARAMETER
Spurious Free Dynamic Range,
SFDR
J
K
ANALOG INPUT
Input Current, Dynamic
Input Current, Static
Input Bandwidth -3dB
Reference Input Current
Input Series Resistance, R
S
Input Capacitance, C
SAMPLE
Input Capacitance, C
HOLD
DIGITAL INPUTS
OEL, OEM, STRT
High-Level Input Voltage, V
IH
Low-Level Input Voltage, V
IL
Input Leakage Current, I
IL
Input Capacitance, C
IN
DIGITAL OUTPUTS
High-Level Output Voltage, V
OH
Low-Level Output Voltage, V
OL
Three-State Leakage, I
OZ
Output Capacitance, C
OUT
CLOCK
High-Level Output Voltage, V
OH
Low-Level Output Voltage, V
OL
Input Current
TIMING
Conversion Time (t
CONV
+ t
ACQ
)
(Includes Acquisition Time)
Clock Frequency
Internal Clock, (CLK = Open)
External CLK (Note 2)
Clock Pulse Width, t
LOW
, t
HIGH
Aperture Delay, t
D
APR
Clock to Data Ready Delay, t
D1
DRDY
Clock to Data Ready Delay, t
D2
DRDY
Start Removal Time, t
R
STRT
Start Setup Time, t
SU
STRT
Start Pulse Width, t
W
STRT
Start to Data Ready Delay, t
D3
DRDY
External CLK (Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
20
200
0.05
100
-
-
-
75
85
10
-
-
300
2
-
35
105
100
30
60
4
65
-
400
1.5
-
50
150
160
-
-
-
105
20
150
0.05
100
-
-
-
75
100
15
-
-
500
1.5
-
70
180
195
-
-
-
120
s
kHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
I
SOURCE
= -100A (Note 2)
I
SINK
= 100A (Note 2)
CLK Only, V
IN
= 0V, 5V
4
-
-
-
-
-
-
1
5
4
-
-
-
1
5
V
V
mA
I
SOURCE
= -400A
I
SINK
= 1.6mA
Except DRDY, V
OUT
= 0V, 5V
Except DRDY
4.6
-
-
-
-
-
-
20
-
0.4
10
-
4.6
-
-
-
-
0.4
10
-
V
V
A
pF
Except CLK, V
IN
= 0V, 5V
2.4
-
-
-
-
-
-
10
-
0.8
10
-
2.4
-
-
-
-
0.8
10
-
V
V
A
pF
In Series with Input C
SAMPLE
During Sample State
During Hold State
At V
IN
= V
REF
+, 0V
Conversion Stopped
-
-
-
-
-
-
-
50
0.4
1
160
420
380
20
100
10
-
-
-
-
-
-
-
-
-
-
-
-
100
10
-
-
-
-
-
A
A
MHz
A
W
pF
pF
TEST CONDITIONS
f
S
=Internal Clock, f
IN
= 1kHz
f
S
= 750kHz, f
IN
= 1kHz
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 750kHz, f
IN
= 1kHz
MIN
-
-
TYP
-75.4
-75.1
-80.9
-79.6
MAX
-
-
-
40
o
C TO 85
o
C
MIN
-
-
MAX
-
-
UNITS
dB
dB
dB
dB
FN3214 Rev 6.00
March 31, 2005
Page 4 of 16
HI5812
Electrical Specifications
V
DD
= V
AA
+ = 5V, V
REF
+ = +4.608V, V
SS
= V
AA
- = V
REF
- = GND, CLK = External 750kHz,
Unless Otherwise Specified
(Continued)
25
o
C
PARAMETER
Clock Delay from Start, t
D
STRT
Output Enable Delay, t
EN
Output Disabled Delay, t
DIS
POWER SUPPLY CHARACTERISTICS
Supply Current, I
DD
+ I
AA
NOTE:
2. Parameter guaranteed by design or characterization, not production tested.
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