CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Supplies = +15V, -15V; V
AH
(Logic Level High) = 2.4V, V
AL
(Logic Level Low) = 0.8V; V
DD
/LLS = GND
(Note 3), Unless Otherwise Specified
TEST
CONDITIONS
TEMP
(
o
C)
25
Full
25
25
25
To 0.1%
To 0.01%
Note 6
Note 7
25
25
25
25
25
25
25
25
Note 3
Note 3
Note 3
Note 3
Full
Full
Full
Full
Full
Full
Note 4
Note 5
Full
25
Full
25
Full
25
Full
25
Full
-8
MIN
-
-
10
-
-
-
-
-
45
-
-
-
-
-
2.4
-
0.7V
DD
-
-
-14
-
-
-
-
-
-
-
-
-
TYP
130
-
20
120
140
250
800
-
-
-
-
-
0.02
-
-
-
-
-
-
-
480
-
0.01
-
0.015
-
0.015
-
-
MAX
175
225
-
175
175
-
-
25
-
5
10
5
-
0.8
-
0.3V
DD
-
1
20
+14
750
1,000
-
50
-
50
-
50
450
-
-
-
45
-
-
-
-
-
2.4
-
0.7V
DD
-
-
-15
-
-
-
-
-
-
-
-
-
MIN
-
-
10
-5
TYP
130
-
20
120
140
250
800
-
-
-
-
-
0.02
-
-
-
-
-
-
-
480
-
0.01
-
0.015
-
0.015
-
-
MAX
175
225
-
175
175
-
-
25
-
5
10
5
-
0.8
-
0.3V
DD
-
1
20
+15
750
1,000
-
50
-
50
-
50
540
UNITS
ns
ns
ns
ns
ns
ns
ns
mV
dB
pF
pF
pF
pF
V
V
V
V
A
A
V
nA
nA
nA
nA
nA
nA
mW
PARAMETER
DYNAMIC CHARACTERISTICS
Access Time, t
A
Break-Before-Make Delay, t
OPEN
Enable Delay (ON), t
ON(EN)
Enable Delay (OFF), t
OFF(EN)
Settling Time
Charge Injection Error
Off Isolation
Channel Input Capacitance, C
S(OFF)
Channel Output Capacitance, C
D(OFF)
Digital Input Capacitance, C
A
Input to Output Capacitance, C
DS(OFF)
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, V
AL
(TTL)
Input High Threshold, V
AH
(TTL)
Input Low Threshold, V
AL
(CMOS)
Input High Threshold, V
AH
(CMOS)
Input Leakage Current, I
AH
(High)
Input Leakage Current, I
AL
(Low)
ANALOG CHANNEL CHARACTERISTICS
Analog Signal Range, V
IN
On Resistance, r
ON
Off Input Leakage Current, l
S(OFF)
Off Output Leakage Current, I
D(OFF)
On Channel Leakage Current, I
D(ON)
POWER SUPPLY CHARACTERISTICS
Power Dissipation, P
D
Full
FN3147 Rev 4.00
January 23, 2006
Page 3 of 8
HI-518
Electrical Specifications
Supplies = +15V, -15V; V
AH
(Logic Level High) = 2.4V, V
AL
(Logic Level Low) = 0.8V; V
DD
/LLS = GND
(Note 3), Unless Otherwise Specified
(Continued)
TEST
CONDITIONS
V
EN
= 2.4V
TEMP
(
o
C)
Full
Full
-8
MIN
-
-
TYP
-
-
MAX
15
15
MIN
-
-
-5
TYP
-
-
MAX
18
18
UNITS
mA
mA
PARAMETER
I+, Current
I-, Current
NOTES:
3. V
DD
/LLS pin = open or grounded for TTL compatibility. V
DD
/LLS pin = V
DD
for CMOS compatibility.
4. At temperatures above 90
o
C, care must be taken to assure V
IN
remains at least 1.0V below the V
SUPPLY
for proper operation.
5. V
IN
=
10V,
I
OUT
= -100A.
6. V
IN
= 0V, C
L
= 100pF, enable input pulse = 3V, f = 500kHz.
7. C
L
= 40pF, R
L
= 1K, V
EN
= 0.8V, V
IN
= 3V
RMS
, f = 500kHz. Due to the pin to pin capacitance between IN 8/4B and OUT B, channel 8/4B
exhibits 60dB of OFF isolation under the above test conditions.
Test Circuits and Waveforms
I
OUT
100A
V
DD
/LLS = GND, Unless Otherwise Specified
EN
V
2
IN
10V
OUT
r
ON
=
V
2
100A
10V
OUT
0.8V
A I
D(OFF)
10V
OUT
OUT
EN
EN
0.8V
10V
2.4V
A
2
A
0
+15V
3.5V
ADDRESS
DRIVE (V
A
)
A
2
/SDS
0V
V
A
50
A
1
A
0
OUTPUT
10%
t
A
2.4V
-10V
EN
V
DD
/LLS
GND
-15V
V+
IN 1
IN 2-7
IN 8
OUTA
OUTB
V-
10
k
50
pF
10V
10V
V
IN
FIGURE 1. ON RESISTANCE TEST CIRCUIT
FIGURE 2. I
D(OFF)
TEST CIRCUIT
(NOTE 8)
I
S(OFF)
A
A I
D(ON)
10V
10V
10V
FIGURE 3. I
S(OFF)
TEST CIRCUIT
(NOTE 8)
FIGURE 4. I
D(ON)
TEST CIRCUIT
(NOTE 8)
50%
+10V
FIGURE 5A. MEASUREMENT POINTS
FIGURE 5. ACCESS TIME
NOTE:
FIGURE 5B. TEST CIRCUIT
8. Two measurements per channel:
10V
and 10V. (Two measurements per device for I
D(OFF)
10V
and 10V.)
FN3147 Rev 4.00
January 23, 2006
Page 4 of 8
HI-518
Test Circuits and Waveforms
V
DD
/LLS = GND, Unless Otherwise Specified
(Continued)
+15V
3.5V
V+
A
2
/SDS
V
A
OUTPUT
IN 1
IN 2-7
50
A
1
A
0
2.4V
EN
V
DD
/LLS
t
OPEN
GND
-15V
IN 8
OUTA
OUTB
V-
800
V
OUT
12.5pF
+5V
0V
ADDRESS
DRIVE (V
A
)
S
1
ON 50%
50% S
8
ON
FIGURE 6A. MEASUREMENT POINTS
FIGURE 6. BREAK-BEFORE-MAKE DELAY
FIGURE 6B. TEST CIRCUIT
+15V
3.5V
50%
ENABLE
50%
DRIVE (V
A
)
V+
0V
A
2
/SDS
IN 1
+10V
90%
OUTPUT
10%
A
1
A
0
50
EN
V
DD
/LLS
GND
IN 2-8
0V
V
A
t
ON(EN)
t
OFF(EN)
OUTA
V-
800
12.5pF
-15V
FIGURE 7A. MEASUREMENT POINTS
FIGURE 7. ENABLE DELAY
FIGURE 7B. TEST CIRCUIT
+15V
2.4V
V+
3V
V
A
V
OUT
0V
V
O
A
0
, A
1
,
A
2
/SDS
OUT
IN
EN
GND
V
DD
/LLS
V-
A OR B
V
OUT
C
L
= 100pF
V
A
-15V
FIGURE 8A. MEASUREMENT POINTS
V
O
is the measured voltage error due to charge injection. The error
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