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Rev. 03-28-07
Page 2
SMSC DS – LAN91C96I
DATASHEET
Non-PCI Single-Chip Full Duplex Ethernet Controller
Table of Contents
Chapter 1
Chapter 2
Chapter 3
3.1
4.1
5.1
5.2
5.3
5.4
General Description ............................................................................................................. 5
Figure 5.1 – Mapping and Paging vs. Receive and Transmit Area ..............................................................................21
Figure 5.2 – Transmit Queues and Mapping................................................................................................................22
Figure 5.3 – Receive Queues and Mapping.................................................................................................................23
Figure 5.4 – LAN91C96i Internal Block Diagram with Data Path .................................................................................24
Figure 5.5 – Logical Address Generation and Relevant Registers...............................................................................25
Figure 6.1 – Data Packet Format .................................................................................................................................29
Figure 8.5 – Driver Send and Allocate Routines ..........................................................................................................67
Figure 8.6 – Interrupt Generation for Transmit; Receive, MMU ...................................................................................71
Figure 9.1 - MMU Packet Number Flow and Relevant Registers .................................................................................76
Figure 10.1 - 64 X 16 Serial EEPROM Map.................................................................................................................83
Figure 12.1 – Local Bus Consecutive Read Cycles.......................................................................................................91
Figure 12.2 – Local Bus Consecutive Write Cycles .......................................................................................................92
FIgure 12.3 – Local Bus Consecutive Read and Write Cycles.......................................................................................93
Figure 12.4 – Data Register Special Read Access ......................................................................................................94
Figure 12.5 – Data Register Special Write Access.......................................................................................................95
Table 5.1 - LAN91C96I Address Space .......................................................................................................................26
Table 5.2 - Bus Transactions In Local Bus Mode .........................................................................................................26
Table 5.5 - Local Bus Mode Defined States (Refer To Table 5.6 For Next States To Wake-Up Events)......................28
Table 5.6 - Local Bus Mode .........................................................................................................................................28
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