HI-DAC80V
TM
Data Sheet
March 2001
File Number
3110.2
12-Bit, Low Cost, Monolithic D/A
Converter
The Hl-DAC80V is a monolithic direct replacement for the
popular DAC80 and AD DAC80. Single chip construction
along with several design innovations make the Hl-DAC80V
the optimum choice for low cost, high reliability applications.
Intersil’ unique Dielectric Isolation (Dl) processing reduces
internal parasitics resulting in fast switching times and
minimum glitch. On board span resistors are provided for
good tracking over temperature, and are laser trimmed to
high accuracy.
Internally the Hl-DAC80V eliminates code dependent ground
currents by routing current from the positive supply to the
internal ground node, as determined by an auxiliary R2R
ladder. This results in a cancellation of code dependent
ground currents allowing virtually zero variation in current
through the package common, pin 21.
The Hl-DAC80V is available as a voltage output device which
is guaranteed over the 0
o
C to 75
o
C temperature range. It
includes a buried zener reference featuring a low temperature
coefficient as well as an on board operational amplifier. The
Hl-DAC80V requires only two power supplies and will operate
in the range of
±
(11.4V to 16.5V).
Features
• DAC 80V Alternative Source
• Monolithic Construction
• Fast Settling Time (Typ) . . . . . . . . . . . . . . . . . . . . . . 1.5µs
• Guaranteed Monotonicity
• Wafer Laser Trimmed Linearity, Gain, Offset
• Span Resistors On-Chip
• On-Board Reference
• Supply Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .
±12V
Applications
• High Speed A/D Converters
• Precision Instrumentation
• CRT Display Generation
Pinout
HI-DAC80V
(PDIP)
TOP VIEW
(MSB) BIT 1 1
BIT 2 2
BIT 3 3
24 6.3V REF OUT
23 GAIN ADJUST
22 +V
S
21 COMMON
20 Â JUNCTION
19 20V RANGE
18 10V RANGE
17 BIPOLAR OFFSET
16 REF INPUT
15 V
OUT
14 -V
S
13 NC
Ordering Information
PART NUMBER
HI3-DAC80V-5
TEMP. RANGE
(
o
C)
0 to 75
PACKAGE
24 Ld PDIP
PKG. NO.
E24.6
BIT 4 4
BIT 5 5
BIT 6 6
BIT 7 7
BIT 8 8
BIT 9 9
BIT 10 10
BIT 11 11
(LSB) BIT 12 12
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
HI-DAC80V
Absolute Maximum Ratings
Power Supply Inputs
+V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20V
-V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20V
Reference
Input (Pin 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +V
S
Output Drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5mA
Digital Inputs (Bits 1 to 12). . . . . . . . . . . . . . . . . . . . . . . . -1V to +V
S
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
Maximum Power Dissipation
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 75
o
C
Die Characteristics
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
Transistor Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
SYSTEM PERFORMANCE
Resolution
ACCURACY
(Note 3)
Linear Error
Differential Linearity Error
Monotonicity
Gain Error
Offset Error
ANALOG OUTPUT
Output Ranges (See Figure 2 and
Table 2)
T
A
= 25
o
C, V
S
±12V
to
±15V
(Note 5), Pin 16 Shorted to Pin 24, Unless Otherwise Specified
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
-
12
Bits
Full Temperature
Full Temperature
Full Temperature
Full Temperature (Notes 2, 4)
Full Temperature (Note 2)
-
-
±
1
/
4
±
1
/
2
Guaranteed
±
1
/
2
±
3
/
4
LSB
LSB
-
±0.1
±0.05
±0.3
±0.15
% FSR
% FSR
-
-
-
-
-
±2.5
±5
±10
0 to 5
0 to 10
-
0.05
Continuous
-
-
-
-
-
-
-
V
V
V
V
V
mA
Ω
-
Output Current
Output Resistance
Short Circuit Duration
DRIFT
(Note 3)
Total Bipolar Drift (Includes Gain,
Offset and Linearity Drifts)
Total Error
Unipolar
Bipolar
Gain
Full Temperature (Note 6)
Full Temperature (Note 6)
With Internal Reference
Without Internal Reference
Full Temperature
To Common
±5
-
-
-
±20
ppm/
o
C
-
-
-
-
±0.08
±0.06
±15
±7
±0.15
±0.1
±30
-
% FSR
% FSR
ppm/
o
C
ppm/
o
C
3
HI-DAC80V
Definitions of Specifications
Digital Inputs
The Hl-DAC80V accepts digital input codes in
complementary binary, complementary offset binary, and
complementary two’s complement binary.
Total Bipolar Drift (TBD) is the variation of output voltage
with temperature, in the bipolar mode of operation. It
represents the net effect of drift in Gain, Offset, Linearity and
Reference Voltage. Total Bipolar Drift values are calculated,
based on measurements as explained above. Gain and
Offset need not be calibrated to zero at 25
o
C. The specified
limits for TBD apply for any input code and for any power
supply setting within the specified operating range.
Settling Time
That interval between application of a digital step input, and
final entry of the analog output within a specified window
about the settled value. Intersil Corporation usually specifies
a unipolar 10V full scale step, to be measured from 50% of
the input digital transition, and a window of
±
1
/
2
LSB about
the final value. The device output is then rated according to
the worst (longest settling) case: low to high, or high to low.
In a 12-bit system
±
1
/
2
LSB =
±0.012%
of FSR.
TABLE 1.
ANALOG OUTPUT
COMPLE-
MENTARY
STRAIGHT
BINARY
COMPLE-
MENTARY
OFFSET
BINARY
COMPLE-
MENTARY
TWO’S
COMPLEMENT
†
Accuracy
Linearity Error
(Short for “Integral Linearity Error.” Also,
sometimes called “Integral Nonlinearity” and “Nonlinearity”.)
The maximum deviation of the actual transfer characteristic
from an ideal straight line. The ideal line is positioned
according to end-point linearity for D/A converter products
from Intersil Corporation, i.e., the line is drawn between the
end-points of the actual transfer characteristic (codes 00...0
and 11...1).
Differential Linearity Error
The difference between one
LSB and the output voltage change corresponding to any
two consecutive codes. A Differential Nonlinearity of
±1
LSB
or less guarantees monotonicity.
Monotonicity
The property of a D/A converter’s transfer
function which guarantees that the output derivative will not
change sign in response to a sequence of increasing (or
decreasing) input codes. That is, the only output response to
a code change is to remain constant, increase for Increasing
code, or decrease for decreasing code.
Total Error
The net output error resulting from all internal
effects (primarily non-ideal Gain, Offset, Linearity and
Reference Voltage). Supply voltages may be set to any
values within the specified operating range. Gain and offset
errors must be calibrated to zero at 25
o
C. Then the specified
limits for Total Error apply for any input code and for any
temperature within the specified operating range.
DIGITAL
INPUT
MSB...LSB
000...000
100...000
111...111
011...111
+ Full Scale
Mid Scale-1 LSB
Zero
+
1
/
2
Full Scale
+ Full Scale
-1 LSB
- Full Scale
Zero
-LSB
+ Full Scale
Zero
- Full Scale
†
Invert MSB with external inverter to obtain CTC Coding.
Thermal Drift
Thermal drift is based on measurements at 25
o
C, at high
(T
H
) and low (T
L
) temperatures. Drift calculations are made
for the high (T
H
-25
o
C) and low (25
o
C-T
L
) ranges, and the
larger of the two values is given as a specification
representing worst case drift.
Gain Drift, Offset Drift, Reference Drift and Total Bipolar Drift
are calculated in parts per million per
o
C as follows:
6
∆FSR ⁄ ∆°C
-
GainDrift
= -------------------------------
×
10
FSR
6
∆Offset ⁄ ∆°C
OffsetDrift
= -------------------------------------
×
10
FSR
Power Supply Sensitivity
Power Supply Sensitivity is a measure of the change in gain
and offset of the D/A converter resulting from a change in
-V
S
, or +V
S
supplies. It is specified under DC conditions and
expressed as full scale range percent of change divided by
power supply percent change.
∆FullScaleRange ×
100
------------------------------------------------------------------
-
FSR
(
Nominal
)
PSS
= ------------------------------------------------------------------
-
∆V
S
×
100
---------------------------------
-
V
S
(Nominal)
∆V
REF
⁄ ( ∆°C )
ReferenceDrift
= ---------------------------------------
×
10
6
V
REF
∆V
O
⁄ ( ∆°C )
6
-
TotalBipolarDrift
= -------------------------------
×
10
FSR
NOTE: FSR = Full Scale Output Voltage - Zero Scale Output
Voltage.
∆FSR
= FSR (T
H
) - FSR (25
o
C),
or FSR (25
o
C) - FSR (T
L
).
V
O
= Steady State response to any input code.
Glitch
A glitch on the output of a D/A converter is a transient spike
resulting from unequal internal ON-OFF switching times.
Worst case glitches usually occur at half-scale, i.e., the
major carry code transition from 011...1 to 100...0 or vice
versa. For example, if turn ON is greater than OFF for
011...1 to 100...0, an intermediate state of 000...0 exists,
such that, the output momentarily glitches toward zero
5
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