CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Short circuits from the output to V+ can cause excessive heating and eventual destruction of the device.
2.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V- = 0V, Unless Otherwise Specified
TEMP
(
o
C)
Full
Full
25
25
CA3290A
MIN
-
-
-
-
-
V
CM
= 1.4V, V+ = 5V
V
CM
= 0V, V+ = +15V, V- = -
15V
V
CM
= 1.4V, V+ = 5V
V
CM
= 0V,
V+ = +15V, V- = -15V
Full
Full
25
25
125
125
25
25
-55
-55
25
25
Full
-
-
-
-
-
-
-
-
-
-
-
-
-
-
25
25
88
TYP
4.5
8.5
4.0
4.0
8
2
7
2
7
2.8
13
3.5
12
0.85
1.62
0.8
1.35
150
103
800
118
MAX
-
-
10
10
-
28
28
25
25
45
45
40
40
1.0
3.0
1.4
3.0
-
-
-
-
MIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
25
88
CA3290
TYP
8.5
8.5
7.5
7.5
8
2
7
2
7
2.8
13
3.5
12
0.85
1.62
0.8
1.35
150
103
800
118
MAX
-
-
20
20
-
32
32
30
30
55
55
50
50
1.6
3.5
1.4
3.0
-
-
-
-
UNITS
mV
mV
mV
mV
µV/
o
C
nA
nA
pA
pA
nA
nA
pA
pA
mA
mA
mA
mA
V/mV
dB
V/mV
dB
PARAMETER
Input Offset Voltage
SYMBOL
V
IO
TEST CONDITIONS
V
CM
= V
O
= 1.4V, V+ = 5V
V
CM
= V
O
= 0V, V+ =
+15V,
V- = -15V
V
CM
= V
O
= 1.4V, V+ = 5V
V
CM
= V
O
= 0V, V+ = +15V,
V- = -15V
Temperature Coefficient
of Input Offset Voltage
Input Offset Current
∆V
IO
/∆T
I
IO
Input Current
I
I
V
CM
= 1.4V, V+ = 5V
V
CM
= 0V, V+ = +15V, V- = -
15V
V
CM
= 1.4V, V+ = 5V
V
CM
= 0V, V+ = +15V, V- = -
15V
Supply Current
I+
R
L
=
∞,
V+ = 5V
R
L
=
∞,
V+ = 30V
R
L
=
∞,
V+ = 5V
R
L
=
∞,
V+ = 30V
Voltage Gain
A
OL
R
L
= 15kΩ, V+ =
+15V,
V- = -15V
R
L
= 15kΩ, V+ = +15V,
V- = -15V
2
CA3290, CA3290A
Electrical Specifications
PARAMETER
Saturation Voltage
V- = 0V, Unless Otherwise Specified
(Continued)
TEMP
(
o
C)
125
-55
25
Full
Full
25
25
25
25
25
25
25
25
25
25
25
25
CA3290A
MIN
-
-
-
-
-
-
-
V+ -3.5
V-
V+ -3.8
V-
-
-
-
6
-
-
-
-
TYP
0.22
0.1
0.12
65
130
100
500
V+ -3.1
V- -1.5
V+ -3.4
V- -1.6
44
100
15
30
1.2
200
500
400
MAX
0.7
-
0.4
-
1k
-
-
-
-
562
562
316
-
-
-
-
-
MIN
-
-
-
-
-
-
-
V+ -3.5
V-
V+ -3.8
V-
-
-
-
6
-
-
-
-
CA3290
TYP
0.22
0.1
0.12
65
130
100
500
V+ -3.1
V- -1.5
V+ -3.4
V- -1.6
44
100
15
30
1.2
200
500
400
MAX
0.7
-
0.4
-
1k
-
-
-
-
562
562
316
-
-
-
-
-
UNITS
V
V
V
nA
nA
pA
pA
V
V
µV/V
µV/V
µV/V
mA
µs
ns
ns
ns
SYMBOL
V
SAT
TEST CONDITIONS
I
SINK
= 4mA, V+ = 5V,
+V
I
= 0V, -V
I
= 1V
I
SINK
= 4mA, V+ = 5V,
+V
I
= 0V, -V
I
= 1V
I
SINK
= 4mA, V+ = 5V,
+V
I
= 0V, -V
I
= 1V
Output Leakage Current
I
OL
V+ = 15V
V+ = 36V
V+ = 15V
V+ = 36V
Common Mode Input
Voltage Range
V
ICR
V
O
= 1.4V, V+ = 5V
V
O
= 0V, V+ = +15V, V- = -15V
Common Mode
Rejection Ratio
Power Supply Rejection
Ratio
Output Sink Current
Response Time Rising
Edge
Response Time Falling
Edge
Large Signal Response
Time
CMRR
V+ = +15V, V- = -15V
V+ = 5V
PSRR
V+ = +15V, V- = -15V
V
O
= 1.4V, V+ = 5V
t
r
t
f
R
L
= 5.1kΩ, V+ = 15V
R
L
= 5.1kΩ, V+ = 15V
R
L
= 5.1kΩ, V+ = 15V
R
L
= 5.1kΩ, V+ = 5V
Test Circuits and Waveforms
C
C
= 2pF
+15V
+15V
1K
+
V
IN
TO 10X
SCOPE
PROBE
-
1K
-15V
WITH C
C
Top Trace
≈
4.5mV/Div. = V
IN
Bottom Trace = 10V/Div. = V
OUT
Time Scale = 5
µ
s/Div.
WITHOUT C
C
Top Trace
≈
4.5mV/Div.
Bottom Trace = 10V/Div.
Time Scale = 5
µ
s/Div.
FIGURE 1. PARASITIC OSCILLATIONS TEST CIRCUIT AND WAVEFORMS
3
CA3290, CA3290A
Test Circuits and Waveforms
INPUT
OVERDRIVE
+15V
GND
INPUT
OVERDRIVE
GND
1K
INPUT
1K
+
5.1K
-
OUTPUT
100mV
OVERDRIVE
20mV
OVERDRIVE
5mV
OVERDRIVE
5mV
OVERDRIVE
20mV
OVERDRIVE
100mV
OVERDRIVE
FIGURE 2. NON-INVERTING COMPARATOR RESPONSE TIME TEST CIRCUIT AND WAVEFORMS
GND
+15V
INPUT
OVERDRIVE
5.1K
+
OUTPUT
1K
5mV
OVERDRIVE
20mV
OVERDRIVE
100mV
OVERDRIVE
GND
INPUT
OVERDRIVE
1K
INPUT
-
100mV
OVERDRIVE
20mV
OVERDRIVE
5mV
OVERDRIVE
FIGURE 3. INVERTING COMPARATOR RESPONSE TIME TEST CIRCUIT AND WAVEFORMS
Circuit Description
The Basic Comparator
Figure 4 shows the basic circuit diagram for one of the two
comparators in the CA3290. It is generically similar to the
industry type “139” comparators, with PMOS transistors
replacing PNP transistors as input stage elements.
Transistors Q
1
through Q
4
comprise the differential input
stage, with Q
5
and Q
6
serving as a mirror connected active
load and differential-to-single-ended converter. The
differential input at Q
1
and Q
4
is amplified so as to toggle Q
6
in accordance with the input signal polarity. For example, if
+V
IN
is greater than -V
IN
, Q
1
, Q
2
, and current mirror
transistors Q
5
and Q
6
will be turned off; Transistors Q
3
, Q
4
,
and Q
7
will be turned on, causing Q
8
to be turned off. The
output is pulled positive when a load resistor is connected
between the output and V+.
In essence, Q
1
and Q
4
function as source followers to drive
Q
2
and Q
3
, respectively, with zener diodes D
1
through D
4
providing gate oxide protection against input voltage
transients (e.g., static electricity). The current flow in Q
1
and
Q
4
is established at approximately 50
µ
A by constant current
sources I
1
and I
3
, respectively. Since Q
1
and Q
4
are
operated with a constant current load, their gate-to-source
voltage drops will be effectively constant as long as the input
voltages are within the common-mode range.
As a result, the input offset voltage (V
GS(Q1)
+ V
BE(Q2)
-
V
BE(Q3)
- V
GS(Q4)
) will not be degraded when a large
differential DC voltage is applied to the device for extended
periods of time at high temperatures.
Additional voltage gain following the first stage is provided
by transistors Q
7
and Q
8
. The collector of Q
8
is open,
offering the user a wide variety of options in applications. An
additional discrete transistor can be added if it becomes
necessary to boost the output sink current capability.
The detailed schematic diagram for one comparator and the
common current source biasing is shown on the front page.
PMOS transistors Q
9
through Q
12
are the current source
4
CA3290, CA3290A
elements identified in Figure 4 as I
1
through I
4
, respectively.
Their gate source potentials (V
GS
) are supplied by a common
bus from the biasing circuit shown in the right hand portion of
the Schematic Diagram. The currents supplied by Q
10
and
Q
12
are twice those supplied by Q
9
and Q
11
. The transistor
geometries are appropriately scaled to provide the requisite
currents with common V
GS
applied to Q
9
through Q
12
.
V+
I
1
50µA
D
1
D
2
I
2
100µA
I
3
50µA
D
3
D
4
Q
8
Q
P4
Q
5
Q
6
V
I
-
Q
7
I
4
100µA
V
O
oscillations unless certain precautions are observed to
minimize the stray capacitive coupling between the input and
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